DE3302013A1 - Divisionsvorrichtung - Google Patents
DivisionsvorrichtungInfo
- Publication number
- DE3302013A1 DE3302013A1 DE19833302013 DE3302013A DE3302013A1 DE 3302013 A1 DE3302013 A1 DE 3302013A1 DE 19833302013 DE19833302013 DE 19833302013 DE 3302013 A DE3302013 A DE 3302013A DE 3302013 A1 DE3302013 A1 DE 3302013A1
- Authority
- DE
- Germany
- Prior art keywords
- register
- divisor
- division
- cycle
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/535—Dividing only
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/4915—Multiplying; Dividing
- G06F7/4917—Dividing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57014967A JPS58132837A (ja) | 1982-02-03 | 1982-02-03 | 10進除算装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE3302013A1 true DE3302013A1 (de) | 1983-08-18 |
| DE3302013C2 DE3302013C2 (OSRAM) | 1988-07-28 |
Family
ID=11875741
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19833302013 Granted DE3302013A1 (de) | 1982-02-03 | 1983-01-21 | Divisionsvorrichtung |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4546447A (OSRAM) |
| JP (1) | JPS58132837A (OSRAM) |
| DE (1) | DE3302013A1 (OSRAM) |
| GB (1) | GB2116757B (OSRAM) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5016210A (en) * | 1989-11-15 | 1991-05-14 | United Technologies Corporation | Binary division of signed operands |
| US5128891A (en) * | 1990-04-02 | 1992-07-07 | Advanced Micro Devices, Inc. | High speed divider with square root capability |
| JPH0731592B2 (ja) * | 1990-11-29 | 1995-04-10 | 株式会社東芝 | 除算回路 |
| US5297073A (en) * | 1992-08-19 | 1994-03-22 | Nec Electronics, Inc. | Integer divide using shift and subtract |
| US5258944A (en) * | 1992-09-01 | 1993-11-02 | Cray Research, Inc. | High performance mantissa divider |
| JP3506753B2 (ja) * | 1994-02-28 | 2004-03-15 | 富士通株式会社 | 除算方法および除算装置 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1549461B2 (de) * | 1967-03-02 | 1974-03-07 | Ibm Deutschland Gmbh, 7000 Stuttgart | Divisionseinrichtung |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB780431A (en) * | 1954-09-17 | 1957-07-31 | British Tabulating Mach Co Ltd | Improvements in or relating to electronic calculating apparatus |
| US3249745A (en) * | 1962-01-09 | 1966-05-03 | Monroe Int | Two-register calculator for performing multiplication and division using identical operational steps |
| FR91575E (fr) * | 1966-01-07 | 1968-07-05 | Commissariat Energie Atomique | Diviseur arithmétique électronique |
| US3591787A (en) * | 1968-01-29 | 1971-07-06 | Ibm | Division system and method |
| US3684879A (en) * | 1970-09-09 | 1972-08-15 | Sperry Rand Corp | Division utilizing multiples of the divisor stored in an addressable memory |
| NL7101258A (OSRAM) * | 1971-01-30 | 1972-08-01 | ||
| JPS52144936A (en) * | 1976-05-28 | 1977-12-02 | Fujitsu Ltd | Decimal system division system |
| US4413326A (en) * | 1978-10-18 | 1983-11-01 | Honeywell Inc. | Floating point division control |
| JPS6029977B2 (ja) * | 1979-01-10 | 1985-07-13 | 株式会社日立製作所 | 2進演算回路 |
| JPS56103739A (en) * | 1980-01-23 | 1981-08-19 | Toshiba Corp | Decimal divider |
| US4320464A (en) * | 1980-05-05 | 1982-03-16 | Control Data Corporation | Binary divider with carry-save adders |
-
1982
- 1982-02-03 JP JP57014967A patent/JPS58132837A/ja active Granted
-
1983
- 1983-01-19 US US06/459,149 patent/US4546447A/en not_active Expired - Lifetime
- 1983-01-21 DE DE19833302013 patent/DE3302013A1/de active Granted
- 1983-01-21 GB GB08301620A patent/GB2116757B/en not_active Expired
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1549461B2 (de) * | 1967-03-02 | 1974-03-07 | Ibm Deutschland Gmbh, 7000 Stuttgart | Divisionseinrichtung |
Also Published As
| Publication number | Publication date |
|---|---|
| DE3302013C2 (OSRAM) | 1988-07-28 |
| US4546447A (en) | 1985-10-08 |
| GB8301620D0 (en) | 1983-02-23 |
| JPS58132837A (ja) | 1983-08-08 |
| GB2116757A (en) | 1983-09-28 |
| JPS6248857B2 (OSRAM) | 1987-10-15 |
| GB2116757B (en) | 1985-12-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE2246968C2 (de) | Einrichtung zur Multiplikation zweier Gleitkommazahlen | |
| DE1956209C3 (de) | Multipliziervorrichtung | |
| DE2523860C3 (de) | Vorrichtung zur digitalen, linearen Interpolation einer fabulierten Funktion | |
| DE3229452C2 (de) | Anordnung zur Durchführung von arithmetischen und logischen Operationen | |
| DE2623986A1 (de) | Parallelrechenwerk | |
| DE2524749C2 (de) | Digitale Filteranordnung | |
| DE2758130C2 (de) | Binärer und dezimaler Hochgeschwindigkeitsaddierer | |
| DE3440680C2 (OSRAM) | ||
| DE3303269C2 (OSRAM) | ||
| DE3447729A1 (de) | Verfahren und vorrichtung zur dezimal-multiplikation | |
| DE3302013A1 (de) | Divisionsvorrichtung | |
| DE1125208B (de) | Elektrisches Vergleichsschaltungssystem | |
| DE3424078C2 (OSRAM) | ||
| DE2203143C3 (de) | Rechenanordnung zum Dividieren von Dezimalzahlen | |
| DE1774771B2 (de) | Anordnung, um wechselweise eine addition oder eine aus einer anzahl logischer funktionen zwischen den stellenwerten zweier binaerwoerter durchzufuehren | |
| DE3785624T2 (de) | Digitaler signalprozessor mit dividierfunktion. | |
| DE3302885A1 (de) | Verfahren und vorrichtung zur multiplikation | |
| DE1549485C3 (de) | Anordnung zur Division binärer Operanden ohne Rückstellung des Restes | |
| DE1549461C3 (OSRAM) | ||
| DE1234055B (de) | Anordnung zur Addition oder Subtraktion | |
| DE1269392B (de) | Einrichtung zur Division von Dezimalziffern | |
| DE2142636A1 (de) | Rechenwerk fuer die durchfuehrung digitaler multiplikationen | |
| DE2432979C3 (de) | Mit gemischter Zahlendarstellung arbeitende Einrichtung zum Multiplizieren zweier komplexer Zahlen und Addieren einer dritten komplexen Zahl zum Produkt | |
| DE2737483A1 (de) | Korrektur-schaltungsanordnung fuer additions- oder substraktionsoperationen mit nicht-hexadezimalen operanden in hexadezimalen rechenwerken | |
| DE1524131C (de) | Binär-dezimales Serien-Serien-Rechenwerk mit Dezimalübertragkorrektor zur Addition und Subtraktion zweier binär-codierter Dezimalzahlen |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OP8 | Request for examination as to paragraph 44 patent law | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition |