DE3277346D1 - Methode of manufacturing a stacked semiconductor device - Google Patents
Methode of manufacturing a stacked semiconductor deviceInfo
- Publication number
- DE3277346D1 DE3277346D1 DE8282305016T DE3277346T DE3277346D1 DE 3277346 D1 DE3277346 D1 DE 3277346D1 DE 8282305016 T DE8282305016 T DE 8282305016T DE 3277346 T DE3277346 T DE 3277346T DE 3277346 D1 DE3277346 D1 DE 3277346D1
- Authority
- DE
- Germany
- Prior art keywords
- methode
- manufacturing
- semiconductor device
- stacked semiconductor
- stacked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
- H01L21/02639—Preparation of substrate for selective deposition
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
- Y10S117/903—Dendrite or web or cage technique
- Y10S117/904—Laser beam
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
- Y10S117/905—Electron beam
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56151484A JPS5853822A (ja) | 1981-09-25 | 1981-09-25 | 積層半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3277346D1 true DE3277346D1 (en) | 1987-10-22 |
Family
ID=15519506
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282305016T Expired DE3277346D1 (en) | 1981-09-25 | 1982-09-23 | Methode of manufacturing a stacked semiconductor device |
Country Status (4)
Country | Link |
---|---|
US (1) | US4569700A (de) |
EP (1) | EP0076101B1 (de) |
JP (1) | JPS5853822A (de) |
DE (1) | DE3277346D1 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5610782A (en) * | 1979-07-06 | 1981-02-03 | Nippon Texas Instr Kk | Demodulating circuit for sound multiplex broadcast |
JPS5890763A (ja) * | 1981-11-25 | 1983-05-30 | Mitsubishi Electric Corp | 半導体装置 |
JPS5892257A (ja) * | 1981-11-27 | 1983-06-01 | Mitsubishi Electric Corp | 半導体装置 |
JPS6014462A (ja) * | 1983-07-05 | 1985-01-25 | Oki Electric Ind Co Ltd | 半導体メモリ素子 |
JPS60189217A (ja) * | 1984-03-09 | 1985-09-26 | Agency Of Ind Science & Technol | 多層soi用シ−ド構造 |
JPS61121433A (ja) * | 1984-11-19 | 1986-06-09 | Sharp Corp | 半導体基板 |
US4663831A (en) * | 1985-10-08 | 1987-05-12 | Motorola, Inc. | Method of forming transistors with poly-sidewall contacts utilizing deposition of polycrystalline and insulating layers combined with selective etching and oxidation of said layers |
KR900008647B1 (ko) * | 1986-03-20 | 1990-11-26 | 후지쓰 가부시끼가이샤 | 3차원 집적회로와 그의 제조방법 |
AU588700B2 (en) * | 1986-06-30 | 1989-09-21 | Canon Kabushiki Kaisha | Semiconductor device and method for producing the same |
JPH0812906B2 (ja) * | 1986-07-11 | 1996-02-07 | キヤノン株式会社 | 光電変換装置の製造方法 |
US5045501A (en) * | 1986-08-25 | 1991-09-03 | Hughes Aircraft Company | Method of forming an integrated circuit structure with multiple common planes |
US4849371A (en) * | 1986-12-22 | 1989-07-18 | Motorola Inc. | Monocrystalline semiconductor buried layers for electrical contacts to semiconductor devices |
JPS6457836A (en) * | 1987-08-27 | 1989-03-06 | Fuotonikusu Kk | Receiver |
JPH02101767A (ja) * | 1988-10-11 | 1990-04-13 | Agency Of Ind Science & Technol | 半導体装置 |
US5191405A (en) * | 1988-12-23 | 1993-03-02 | Matsushita Electric Industrial Co., Ltd. | Three-dimensional stacked lsi |
FR2645681B1 (fr) * | 1989-04-07 | 1994-04-08 | Thomson Csf | Dispositif d'interconnexion verticale de pastilles de circuits integres et son procede de fabrication |
DE4417916A1 (de) * | 1994-05-24 | 1995-11-30 | Telefunken Microelectron | Verfahren zur Herstellung eines Bipolartransistors |
US20060113596A1 (en) * | 2004-12-01 | 2006-06-01 | Samsung Electronics Co., Ltd. | Single crystal substrate and method of fabricating the same |
US7776718B2 (en) * | 2007-06-25 | 2010-08-17 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing semiconductor substrate with reduced gap size between single-crystalline layers |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1417088A (fr) * | 1963-12-16 | 1965-11-05 | Rca Corp | Pastilles composites isolantes et semi-conductrices |
DE1589705A1 (de) * | 1967-11-15 | 1970-04-30 | Itt Ind Gmbh Deutsche | Mehrere elektrische Funktionsstufen enthaltende integrierte Schaltung |
DE2832012A1 (de) * | 1978-07-20 | 1980-01-31 | Siemens Ag | Verfahren zum herstellen einer dreidimensionalen integrierten schaltung |
NL7810549A (nl) * | 1978-10-23 | 1980-04-25 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleider- inrichting. |
EP0020135A1 (de) * | 1979-05-29 | 1980-12-10 | Massachusetts Institute Of Technology | Dreidimensionale Integration durch graphische Epitaxie |
JPS5667923A (en) * | 1979-11-07 | 1981-06-08 | Toshiba Corp | Preparation method of semiconductor system |
US4323417A (en) * | 1980-05-06 | 1982-04-06 | Texas Instruments Incorporated | Method of producing monocrystal on insulator |
US4319954A (en) * | 1981-02-27 | 1982-03-16 | Rca Corporation | Method of forming polycrystalline silicon lines and vias on a silicon substrate |
JPS57155764A (en) * | 1981-03-20 | 1982-09-25 | Fujitsu Ltd | Manufacture of semiconductor device |
EP0073487B1 (de) * | 1981-08-31 | 1988-07-20 | Kabushiki Kaisha Toshiba | Verfahren zur Herstellung einer dreidimensionalen Halbleitervorrichtung |
JPS5861622A (ja) * | 1981-10-09 | 1983-04-12 | Hitachi Ltd | 単結晶薄膜の製造方法 |
JPS59108313A (ja) * | 1982-12-13 | 1984-06-22 | Mitsubishi Electric Corp | 半導体単結晶層の製造方法 |
-
1981
- 1981-09-25 JP JP56151484A patent/JPS5853822A/ja active Pending
-
1982
- 1982-09-23 EP EP82305016A patent/EP0076101B1/de not_active Expired
- 1982-09-23 DE DE8282305016T patent/DE3277346D1/de not_active Expired
-
1985
- 1985-07-01 US US06/750,245 patent/US4569700A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS5853822A (ja) | 1983-03-30 |
EP0076101A3 (en) | 1984-09-05 |
EP0076101B1 (de) | 1987-09-16 |
US4569700A (en) | 1986-02-11 |
EP0076101A2 (de) | 1983-04-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |