DE3175448D1 - Method for making a self-aligned field effect transistor integrated circuit structure - Google Patents

Method for making a self-aligned field effect transistor integrated circuit structure

Info

Publication number
DE3175448D1
DE3175448D1 DE8181104806T DE3175448T DE3175448D1 DE 3175448 D1 DE3175448 D1 DE 3175448D1 DE 8181104806 T DE8181104806 T DE 8181104806T DE 3175448 T DE3175448 T DE 3175448T DE 3175448 D1 DE3175448 D1 DE 3175448D1
Authority
DE
Germany
Prior art keywords
self
making
integrated circuit
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181104806T
Other languages
German (de)
English (en)
Inventor
Chakrapani Gajanan Jambotkar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3175448D1 publication Critical patent/DE3175448D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0273—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H10D62/021—Forming source or drain recesses by etching e.g. recessing by etching and then refilling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
DE8181104806T 1980-07-08 1981-06-23 Method for making a self-aligned field effect transistor integrated circuit structure Expired DE3175448D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/167,172 US4378627A (en) 1980-07-08 1980-07-08 Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes

Publications (1)

Publication Number Publication Date
DE3175448D1 true DE3175448D1 (en) 1986-11-13

Family

ID=22606247

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181104806T Expired DE3175448D1 (en) 1980-07-08 1981-06-23 Method for making a self-aligned field effect transistor integrated circuit structure

Country Status (4)

Country Link
US (1) US4378627A (enExample)
EP (1) EP0043944B1 (enExample)
JP (1) JPS5732674A (enExample)
DE (1) DE3175448D1 (enExample)

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US4939154A (en) * 1987-03-25 1990-07-03 Seiko Instruments Inc. Method of fabricating an insulated gate semiconductor device having a self-aligned gate
FR2618011B1 (fr) * 1987-07-10 1992-09-18 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire
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JPH0289323A (ja) * 1988-09-27 1990-03-29 Nec Corp Ｍｉｓ型電界効果トランジスタの製造方法
US5079180A (en) * 1988-12-22 1992-01-07 Texas Instruments Incorporated Method of fabricating a raised source/drain transistor
US4945070A (en) * 1989-01-24 1990-07-31 Harris Corporation Method of making cmos with shallow source and drain junctions
US5001082A (en) * 1989-04-12 1991-03-19 Mcnc Self-aligned salicide process for forming semiconductor devices and devices formed thereby
KR940005729B1 (ko) * 1989-06-13 1994-06-23 삼성전자 주식회사 디램셀의 제조방법 및 구조
US5093275A (en) * 1989-09-22 1992-03-03 The Board Of Regents, The University Of Texas System Method for forming hot-carrier suppressed sub-micron MISFET device
US5012306A (en) * 1989-09-22 1991-04-30 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron MISFET device
JPH03296247A (ja) * 1990-04-13 1991-12-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5024971A (en) * 1990-08-20 1991-06-18 Motorola, Inc. Method for patterning submicron openings using an image reversal layer of material
US5028557A (en) * 1990-08-27 1991-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a reverse self-aligned BIMOS transistor integrated circuit
US5175606A (en) * 1990-08-27 1992-12-29 Taiwan Semiconductor Manufacturing Company Reverse self-aligned BiMOS transistor integrated circuit
US5235204A (en) * 1990-08-27 1993-08-10 Taiwan Semiconductor Manufacturing Company Reverse self-aligned transistor integrated circuit
US5071780A (en) * 1990-08-27 1991-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse self-aligned transistor integrated circuit
US5242858A (en) * 1990-09-07 1993-09-07 Canon Kabushiki Kaisha Process for preparing semiconductor device by use of a flattening agent and diffusion
JPH04280436A (ja) * 1990-09-28 1992-10-06 Motorola Inc 相補型自己整合ｈｆｅｔの製造方法
AT404524B (de) * 1991-09-03 1998-12-28 Austria Mikrosysteme Int Verfahren zur herstellung von selbstausgerichteten, lateralen und vertikalen halbleiterbauelementen
US5212106A (en) * 1992-05-07 1993-05-18 Advanced Micro Devices, Inc. Optimizing doping control in short channel MOS
US5215937A (en) * 1992-05-07 1993-06-01 Advanced Micro Devices, Inc. Optimizing doping control in short channel MOS
US5270234A (en) * 1992-10-30 1993-12-14 International Business Machines Corporation Deep submicron transistor fabrication method
US5466615A (en) * 1993-08-19 1995-11-14 Taiwan Semiconductor Manufacturing Company Ltd. Silicon damage free process for double poly emitter and reverse MOS in BiCMOS application
US5434093A (en) * 1994-08-10 1995-07-18 Intel Corporation Inverted spacer transistor
JP2720796B2 (ja) * 1994-11-15 1998-03-04 日本電気株式会社 半導体装置の製造方法
EP0849782A1 (en) * 1996-12-20 1998-06-24 Siemens Aktiengesellschaft A mos transistor
US5879998A (en) * 1997-07-09 1999-03-09 Advanced Micro Devices, Inc. Adaptively controlled, self-aligned, short channel device and method for manufacturing same
US5776821A (en) * 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US5970354A (en) * 1997-12-08 1999-10-19 Advanced Micro Devices, Inc. Poly recessed fabrication method for defining high performance MOSFETS
US6774001B2 (en) * 1998-10-13 2004-08-10 Stmicroelectronics, Inc. Self-aligned gate and method
US6159808A (en) * 1999-11-12 2000-12-12 United Semiconductor Corp. Method of forming self-aligned DRAM cell
TW490745B (en) * 2000-05-15 2002-06-11 Ibm Self-aligned double gate MOSFET with separate gates
US6982460B1 (en) 2000-07-07 2006-01-03 International Business Machines Corporation Self-aligned gate MOSFET with separate gates
US6902867B2 (en) * 2002-10-02 2005-06-07 Lexmark International, Inc. Ink jet printheads and methods therefor

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Also Published As

Publication number Publication date
EP0043944B1 (en) 1986-10-08
EP0043944A2 (en) 1982-01-20
JPS5732674A (en) 1982-02-22
JPH033389B2 (enExample) 1991-01-18
US4378627A (en) 1983-04-05
EP0043944A3 (en) 1983-07-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee