DE3175448D1 - Method for making a self-aligned field effect transistor integrated circuit structure - Google Patents

Method for making a self-aligned field effect transistor integrated circuit structure

Info

Publication number
DE3175448D1
DE3175448D1 DE8181104806T DE3175448T DE3175448D1 DE 3175448 D1 DE3175448 D1 DE 3175448D1 DE 8181104806 T DE8181104806 T DE 8181104806T DE 3175448 T DE3175448 T DE 3175448T DE 3175448 D1 DE3175448 D1 DE 3175448D1
Authority
DE
Germany
Prior art keywords
self
making
integrated circuit
field effect
effect transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181104806T
Other languages
English (en)
Inventor
Chakrapani Gajanan Jambotkar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3175448D1 publication Critical patent/DE3175448D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66606—Lateral single gate silicon transistors with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
DE8181104806T 1980-07-08 1981-06-23 Method for making a self-aligned field effect transistor integrated circuit structure Expired DE3175448D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/167,172 US4378627A (en) 1980-07-08 1980-07-08 Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes

Publications (1)

Publication Number Publication Date
DE3175448D1 true DE3175448D1 (en) 1986-11-13

Family

ID=22606247

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181104806T Expired DE3175448D1 (en) 1980-07-08 1981-06-23 Method for making a self-aligned field effect transistor integrated circuit structure

Country Status (4)

Country Link
US (1) US4378627A (de)
EP (1) EP0043944B1 (de)
JP (1) JPS5732674A (de)
DE (1) DE3175448D1 (de)

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FR2529714A1 (fr) * 1982-07-01 1984-01-06 Commissariat Energie Atomique Procede de realisation de l'oxyde de champ d'un circuit integre
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US4551906A (en) * 1983-12-12 1985-11-12 International Business Machines Corporation Method for making self-aligned lateral bipolar transistors
US4546535A (en) * 1983-12-12 1985-10-15 International Business Machines Corporation Method of making submicron FET structure
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
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JPS6182482A (ja) * 1984-09-29 1986-04-26 Toshiba Corp ＧａＡｓ電界効果トランジスタの製造方法
US4571817A (en) * 1985-03-15 1986-02-25 Motorola, Inc. Method of making closely spaced contacts to PN-junction using stacked polysilicon layers, differential etching and ion implantations
US4666737A (en) * 1986-02-11 1987-05-19 Harris Corporation Via metallization using metal fillets
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US4939154A (en) * 1987-03-25 1990-07-03 Seiko Instruments Inc. Method of fabricating an insulated gate semiconductor device having a self-aligned gate
FR2618011B1 (fr) * 1987-07-10 1992-09-18 Commissariat Energie Atomique Procede de fabrication d'une cellule de memoire
US4818713A (en) * 1987-10-20 1989-04-04 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques useful in fabricating semiconductor devices having submicron features
JPH0251238A (ja) * 1988-08-12 1990-02-21 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JPH0289323A (ja) * 1988-09-27 1990-03-29 Nec Corp Ｍｉｓ型電界効果トランジスタの製造方法
US5079180A (en) * 1988-12-22 1992-01-07 Texas Instruments Incorporated Method of fabricating a raised source/drain transistor
US4945070A (en) * 1989-01-24 1990-07-31 Harris Corporation Method of making cmos with shallow source and drain junctions
US5001082A (en) * 1989-04-12 1991-03-19 Mcnc Self-aligned salicide process for forming semiconductor devices and devices formed thereby
KR940005729B1 (ko) * 1989-06-13 1994-06-23 삼성전자 주식회사 디램셀의 제조방법 및 구조
US5093275A (en) * 1989-09-22 1992-03-03 The Board Of Regents, The University Of Texas System Method for forming hot-carrier suppressed sub-micron MISFET device
US5012306A (en) * 1989-09-22 1991-04-30 Board Of Regents, The University Of Texas System Hot-carrier suppressed sub-micron MISFET device
JPH03296247A (ja) * 1990-04-13 1991-12-26 Mitsubishi Electric Corp 半導体装置およびその製造方法
US5024971A (en) * 1990-08-20 1991-06-18 Motorola, Inc. Method for patterning submicron openings using an image reversal layer of material
US5235204A (en) * 1990-08-27 1993-08-10 Taiwan Semiconductor Manufacturing Company Reverse self-aligned transistor integrated circuit
US5175606A (en) * 1990-08-27 1992-12-29 Taiwan Semiconductor Manufacturing Company Reverse self-aligned BiMOS transistor integrated circuit
US5071780A (en) * 1990-08-27 1991-12-10 Taiwan Semiconductor Manufacturing Company, Ltd. Reverse self-aligned transistor integrated circuit
US5028557A (en) * 1990-08-27 1991-07-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method of making a reverse self-aligned BIMOS transistor integrated circuit
US5242858A (en) * 1990-09-07 1993-09-07 Canon Kabushiki Kaisha Process for preparing semiconductor device by use of a flattening agent and diffusion
JPH04280436A (ja) * 1990-09-28 1992-10-06 Motorola Inc 相補型自己整合ｈｆｅｔの製造方法
AT404524B (de) * 1991-09-03 1998-12-28 Austria Mikrosysteme Int Verfahren zur herstellung von selbstausgerichteten, lateralen und vertikalen halbleiterbauelementen
US5215937A (en) * 1992-05-07 1993-06-01 Advanced Micro Devices, Inc. Optimizing doping control in short channel MOS
US5212106A (en) * 1992-05-07 1993-05-18 Advanced Micro Devices, Inc. Optimizing doping control in short channel MOS
US5270234A (en) * 1992-10-30 1993-12-14 International Business Machines Corporation Deep submicron transistor fabrication method
US5466615A (en) * 1993-08-19 1995-11-14 Taiwan Semiconductor Manufacturing Company Ltd. Silicon damage free process for double poly emitter and reverse MOS in BiCMOS application
US5434093A (en) * 1994-08-10 1995-07-18 Intel Corporation Inverted spacer transistor
JP2720796B2 (ja) * 1994-11-15 1998-03-04 日本電気株式会社 半導体装置の製造方法
EP0849782A1 (de) * 1996-12-20 1998-06-24 Siemens Aktiengesellschaft Ein MOS-Transistor
US5879998A (en) * 1997-07-09 1999-03-09 Advanced Micro Devices, Inc. Adaptively controlled, self-aligned, short channel device and method for manufacturing same
US5776821A (en) * 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US5970354A (en) * 1997-12-08 1999-10-19 Advanced Micro Devices, Inc. Poly recessed fabrication method for defining high performance MOSFETS
US6774001B2 (en) * 1998-10-13 2004-08-10 Stmicroelectronics, Inc. Self-aligned gate and method
US6159808A (en) * 1999-11-12 2000-12-12 United Semiconductor Corp. Method of forming self-aligned DRAM cell
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TW490745B (en) * 2000-05-15 2002-06-11 Ibm Self-aligned double gate MOSFET with separate gates
US6902867B2 (en) * 2002-10-02 2005-06-07 Lexmark International, Inc. Ink jet printheads and methods therefor

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Also Published As

Publication number Publication date
EP0043944A2 (de) 1982-01-20
EP0043944B1 (de) 1986-10-08
US4378627A (en) 1983-04-05
JPS5732674A (en) 1982-02-22
JPH033389B2 (de) 1991-01-18
EP0043944A3 (en) 1983-07-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee