DE3104024C2 - - Google Patents

Info

Publication number
DE3104024C2
DE3104024C2 DE19813104024 DE3104024A DE3104024C2 DE 3104024 C2 DE3104024 C2 DE 3104024C2 DE 19813104024 DE19813104024 DE 19813104024 DE 3104024 A DE3104024 A DE 3104024A DE 3104024 C2 DE3104024 C2 DE 3104024C2
Authority
DE
Germany
Prior art keywords
etched
chlorine
etching
silicon
polysilicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE19813104024
Other languages
German (de)
English (en)
Other versions
DE3104024A1 (de
Inventor
Dan Short Hills N.J. Us Maydan
David Nin-Kou Warren Township N.J. Us Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Technologies Inc filed Critical AT&T Technologies Inc
Publication of DE3104024A1 publication Critical patent/DE3104024A1/de
Application granted granted Critical
Publication of DE3104024C2 publication Critical patent/DE3104024C2/de
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • CCHEMISTRY; METALLURGY
    • C04CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04BLIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/53After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone involving the removal of at least part of the materials of the treated article, e.g. etching, drying of hardened concrete
    • C04B41/5338Etching
    • C04B41/5346Dry etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Plasma & Fusion (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Structural Engineering (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
DE19813104024 1980-02-06 1981-02-05 Reaktives zerstaeubungsaetzen von silicium Granted DE3104024A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11910380A 1980-02-06 1980-02-06

Publications (2)

Publication Number Publication Date
DE3104024A1 DE3104024A1 (de) 1981-12-17
DE3104024C2 true DE3104024C2 (enrdf_load_stackoverflow) 1988-08-18

Family

ID=22382565

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19813104024 Granted DE3104024A1 (de) 1980-02-06 1981-02-05 Reaktives zerstaeubungsaetzen von silicium

Country Status (6)

Country Link
JP (1) JPS56130928A (enrdf_load_stackoverflow)
CA (1) CA1148895A (enrdf_load_stackoverflow)
DE (1) DE3104024A1 (enrdf_load_stackoverflow)
FR (1) FR2478421A1 (enrdf_load_stackoverflow)
GB (1) GB2068286B (enrdf_load_stackoverflow)
NL (1) NL190592C (enrdf_load_stackoverflow)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3606959A1 (de) * 1986-03-04 1987-09-10 Leybold Heraeus Gmbh & Co Kg Vorrichtung zur plasmabehandlung von substraten in einer durch hochfrequenz angeregten plasmaentladung
JPH0831439B2 (ja) * 1986-03-05 1996-03-27 株式会社東芝 反応性イオンエッチング方法
DE3935189A1 (de) * 1989-10-23 1991-05-08 Leybold Ag Verfahren und vorrichtung zur behandlung von werkstuecken durch reaktives ionenaetzen
KR930008580B1 (ko) * 1990-06-22 1993-09-09 현대전자산업 주식회사 표면적이 극대화된 실리콘층 및 그 제조방법

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4104086A (en) * 1977-08-15 1978-08-01 International Business Machines Corporation Method for forming isolated regions of silicon utilizing reactive ion etching
US4226665A (en) * 1978-07-31 1980-10-07 Bell Telephone Laboratories, Incorporated Device fabrication by plasma etching

Also Published As

Publication number Publication date
DE3104024A1 (de) 1981-12-17
CA1148895A (en) 1983-06-28
NL8100560A (nl) 1981-09-01
FR2478421B1 (enrdf_load_stackoverflow) 1983-12-23
GB2068286A (en) 1981-08-12
GB2068286B (en) 1984-07-11
FR2478421A1 (fr) 1981-09-18
NL190592B (nl) 1993-12-01
NL190592C (nl) 1994-05-02
JPS56130928A (en) 1981-10-14

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8127 New person/name/address of the applicant

Owner name: AT & T TECHNOLOGIES, INC., NEW YORK, N.Y., US

8128 New person/name/address of the agent

Representative=s name: BLUMBACH, P., DIPL.-ING., 6200 WIESBADEN WESER, W.

D2 Grant after examination
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN