DE2946633C2 - - Google Patents
Info
- Publication number
- DE2946633C2 DE2946633C2 DE2946633A DE2946633A DE2946633C2 DE 2946633 C2 DE2946633 C2 DE 2946633C2 DE 2946633 A DE2946633 A DE 2946633A DE 2946633 A DE2946633 A DE 2946633A DE 2946633 C2 DE2946633 C2 DE 2946633C2
- Authority
- DE
- Germany
- Prior art keywords
- column
- decoder
- row
- signal
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4087—Address decoders, e.g. bit - or word line decoders; Multiple line decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1978158800U JPS5575899U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1978-11-20 | 1978-11-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE2946633A1 DE2946633A1 (de) | 1980-06-04 |
| DE2946633C2 true DE2946633C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1988-12-22 |
Family
ID=15679619
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19792946633 Granted DE2946633A1 (de) | 1978-11-20 | 1979-11-19 | Speichervorrichtung mit hochgeschwindigkeits-speicherzellenwaehleinrichtung |
Country Status (3)
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57118599U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * | 1981-01-14 | 1982-07-23 | ||
| JPS57198592A (en) * | 1981-05-29 | 1982-12-06 | Hitachi Ltd | Semiconductor memory device |
| JPS5954096A (ja) * | 1982-09-22 | 1984-03-28 | Hitachi Ltd | ダイナミツク型ｍｏｓｒａｍ |
| JPS5956284A (ja) * | 1982-09-24 | 1984-03-31 | Hitachi Micro Comput Eng Ltd | 半導体記憶装置 |
| JPS6059588A (ja) * | 1983-09-12 | 1985-04-05 | Hitachi Ltd | 半導体記憶装置 |
| US6563743B2 (en) | 2000-11-27 | 2003-05-13 | Hitachi, Ltd. | Semiconductor device having dummy cells and semiconductor device having dummy cells for redundancy |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3760384A (en) * | 1970-10-27 | 1973-09-18 | Cogar Corp | Fet memory chip including fet devices therefor and fabrication method |
| JPS5914827B2 (ja) * | 1976-08-23 | 1984-04-06 | 株式会社日立製作所 | アドレス選択システム |
| JPS5333542A (en) * | 1976-09-10 | 1978-03-29 | Hitachi Ltd | Signal detection circuit |
| US4110840A (en) * | 1976-12-22 | 1978-08-29 | Motorola Inc. | Sense line charging system for random access memory |
| US4208730A (en) * | 1978-08-07 | 1980-06-17 | Rca Corporation | Precharge circuit for memory array |
-
1978
- 1978-11-20 JP JP1978158800U patent/JPS5575899U/ja active Pending
-
1979
- 1979-11-16 US US06/094,927 patent/US4316265A/en not_active Expired - Lifetime
- 1979-11-19 DE DE19792946633 patent/DE2946633A1/de active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5575899U (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) | 1980-05-24 |
| DE2946633A1 (de) | 1980-06-04 |
| US4316265A (en) | 1982-02-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OD | Request for examination | ||
| D2 | Grant after examination | ||
| 8364 | No opposition during term of opposition |