DE2804525C2 - - Google Patents

Info

Publication number
DE2804525C2
DE2804525C2 DE2804525A DE2804525A DE2804525C2 DE 2804525 C2 DE2804525 C2 DE 2804525C2 DE 2804525 A DE2804525 A DE 2804525A DE 2804525 A DE2804525 A DE 2804525A DE 2804525 C2 DE2804525 C2 DE 2804525C2
Authority
DE
Germany
Prior art keywords
doping
zone
base
base zone
semiconductor region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2804525A
Other languages
German (de)
English (en)
Other versions
DE2804525A1 (de
Inventor
Wolfgang Dr. 8000 Muenchen De Werner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE19782804525 priority Critical patent/DE2804525A1/de
Publication of DE2804525A1 publication Critical patent/DE2804525A1/de
Application granted granted Critical
Publication of DE2804525C2 publication Critical patent/DE2804525C2/de
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65Integrated injection logic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/40Vertical BJTs
    • H10D10/421Vertical BJTs having both emitter-base and base-collector junctions ending at the same surface of the body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/125Shapes of junctions between the regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
DE19782804525 1978-02-02 1978-02-02 Verfahren zur herstellung eines transistors im verband einer monolithisch integrierten halbleiterschaltung Granted DE2804525A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE19782804525 DE2804525A1 (de) 1978-02-02 1978-02-02 Verfahren zur herstellung eines transistors im verband einer monolithisch integrierten halbleiterschaltung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19782804525 DE2804525A1 (de) 1978-02-02 1978-02-02 Verfahren zur herstellung eines transistors im verband einer monolithisch integrierten halbleiterschaltung

Publications (2)

Publication Number Publication Date
DE2804525A1 DE2804525A1 (de) 1979-08-16
DE2804525C2 true DE2804525C2 (enExample) 1989-09-14

Family

ID=6031016

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19782804525 Granted DE2804525A1 (de) 1978-02-02 1978-02-02 Verfahren zur herstellung eines transistors im verband einer monolithisch integrierten halbleiterschaltung

Country Status (1)

Country Link
DE (1) DE2804525A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0107851A1 (en) * 1982-10-29 1984-05-09 Tektronix, Inc. Manufacture of semiconductor devices by the planar method

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4067037A (en) * 1976-04-12 1978-01-03 Massachusetts Institute Of Technology Transistor having high ft at low currents

Also Published As

Publication number Publication date
DE2804525A1 (de) 1979-08-16

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee