DE2753607C2 - - Google Patents

Info

Publication number
DE2753607C2
DE2753607C2 DE2753607A DE2753607A DE2753607C2 DE 2753607 C2 DE2753607 C2 DE 2753607C2 DE 2753607 A DE2753607 A DE 2753607A DE 2753607 A DE2753607 A DE 2753607A DE 2753607 C2 DE2753607 C2 DE 2753607C2
Authority
DE
Germany
Prior art keywords
transistor
circuit
conductor
control signal
addressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE2753607A
Other languages
German (de)
English (en)
Other versions
DE2753607A1 (de
Inventor
Charles Raymond Cupertino Calif. Us Schmitz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of DE2753607A1 publication Critical patent/DE2753607A1/de
Application granted granted Critical
Publication of DE2753607C2 publication Critical patent/DE2753607C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
DE19772753607 1976-12-01 1977-12-01 Monolithischer integrierter bipolarer speicher Granted DE2753607A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US74636276A 1976-12-01 1976-12-01

Publications (2)

Publication Number Publication Date
DE2753607A1 DE2753607A1 (de) 1978-06-08
DE2753607C2 true DE2753607C2 (enExample) 1990-05-17

Family

ID=25000519

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19772753607 Granted DE2753607A1 (de) 1976-12-01 1977-12-01 Monolithischer integrierter bipolarer speicher

Country Status (5)

Country Link
JP (1) JPS5831679B2 (enExample)
DE (1) DE2753607A1 (enExample)
FR (1) FR2373124A1 (enExample)
GB (1) GB1547730A (enExample)
IT (1) IT1090712B (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55142475A (en) * 1979-04-23 1980-11-07 Fujitsu Ltd Decoder circuit
JPS5667964A (en) * 1979-11-08 1981-06-08 Nec Corp Integrated circuit
US4385368A (en) * 1980-11-24 1983-05-24 Raytheon Company Programmable read only memory
JPS5884549A (ja) * 1981-11-16 1983-05-20 Nec Corp 無線選択呼出受信機
US4686651A (en) * 1984-11-15 1987-08-11 Raytheon Company Power switched read-only memory
DE10051164B4 (de) * 2000-10-16 2007-10-25 Infineon Technologies Ag Verfahren zur Maskierung von DQ-Bits

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3599182A (en) * 1969-01-15 1971-08-10 Ibm Means for reducing power consumption in a memory device
US3680061A (en) * 1970-04-30 1972-07-25 Ncr Co Integrated circuit bipolar random access memory system with low stand-by power consumption
US3859637A (en) * 1973-06-28 1975-01-07 Ibm On-chip auxiliary latch for down-powering array latch decoders
US3867644A (en) * 1974-01-07 1975-02-18 Signetics Corp High speed low power schottky integrated logic gate circuit with current boost
US3979611A (en) * 1975-02-06 1976-09-07 Rca Corporation Transistor switching circuit

Also Published As

Publication number Publication date
FR2373124B1 (enExample) 1984-06-22
JPS5369552A (en) 1978-06-21
IT1090712B (it) 1985-06-26
GB1547730A (en) 1979-06-27
FR2373124A1 (fr) 1978-06-30
JPS5831679B2 (ja) 1983-07-07
DE2753607A1 (de) 1978-06-08

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee