DE2708702A1 - Selektionstreiberschaltung - Google Patents

Selektionstreiberschaltung

Info

Publication number
DE2708702A1
DE2708702A1 DE19772708702 DE2708702A DE2708702A1 DE 2708702 A1 DE2708702 A1 DE 2708702A1 DE 19772708702 DE19772708702 DE 19772708702 DE 2708702 A DE2708702 A DE 2708702A DE 2708702 A1 DE2708702 A1 DE 2708702A1
Authority
DE
Germany
Prior art keywords
transistor
circuit
gate
transistors
selection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19772708702
Other languages
German (de)
English (en)
Inventor
Dominic Patrick Spampinato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2708702A1 publication Critical patent/DE2708702A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
DE19772708702 1976-03-08 1977-03-01 Selektionstreiberschaltung Withdrawn DE2708702A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/665,144 US4074237A (en) 1976-03-08 1976-03-08 Word line clamping circuit and decoder

Publications (1)

Publication Number Publication Date
DE2708702A1 true DE2708702A1 (de) 1977-09-15

Family

ID=24668908

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19772708702 Withdrawn DE2708702A1 (de) 1976-03-08 1977-03-01 Selektionstreiberschaltung

Country Status (6)

Country Link
US (1) US4074237A (US06724976-20040420-M00002.png)
JP (1) JPS52108741A (US06724976-20040420-M00002.png)
CA (1) CA1097814A (US06724976-20040420-M00002.png)
DE (1) DE2708702A1 (US06724976-20040420-M00002.png)
FR (1) FR2344092A1 (US06724976-20040420-M00002.png)
IT (1) IT1118018B (US06724976-20040420-M00002.png)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3037130A1 (de) * 1979-10-04 1981-04-09 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Halbleiter-speicherschaltung und adressenbezeichnungsschaltung dafuer
DE3142557A1 (de) * 1980-10-29 1982-08-12 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Integrierte halbleiterschaltungsanordnung

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6023432B2 (ja) * 1977-12-09 1985-06-07 株式会社日立製作所 Ｍｏｓメモリ
JPS5493335A (en) * 1977-12-30 1979-07-24 Fujitsu Ltd Decoder circuit
US4259731A (en) * 1979-11-14 1981-03-31 Motorola, Inc. Quiet row selection circuitry
JPS56101687A (en) * 1979-12-27 1981-08-14 Fujitsu Ltd Semiconductor memory circuit
US4360902A (en) * 1980-06-02 1982-11-23 Mostek Corporation Semiconductor memory decoder with nonselected row line hold down
EP0052605A1 (en) * 1980-06-02 1982-06-02 Mostek Corporation Semiconductor memory decoder with nonselected row line hold down
JPS57501002A (US06724976-20040420-M00002.png) * 1980-06-02 1982-06-03
DE3104150A1 (de) * 1981-02-06 1982-09-09 Siemens AG, 1000 Berlin und 8000 München Monolithisch integrierte mos-halbleiterspeicher
JPS58207718A (ja) * 1982-05-28 1983-12-03 Nec Corp 出力回路
JPS5960794A (ja) * 1982-09-29 1984-04-06 Fujitsu Ltd ダイナミツク型半導体記憶装置
US4567581A (en) * 1982-12-22 1986-01-28 At&T Bell Laboratories Column decoder circuit for use with memory using multiplexed row and column address lines
US4514829A (en) * 1982-12-30 1985-04-30 International Business Machines Corporation Word line decoder and driver circuits for high density semiconductor memory
JPH03250494A (ja) * 1990-02-27 1991-11-08 Ricoh Co Ltd 半導体記憶装置
US5864507A (en) * 1996-12-18 1999-01-26 Cypress Semiconductor Corporation Dual level wordline clamp for reduced memory cell current
JPH10214497A (ja) * 1997-01-31 1998-08-11 Mitsubishi Electric Corp 半導体記憶装置
JP4617840B2 (ja) * 2004-11-17 2011-01-26 日本電気株式会社 ブートストラップ回路及びその駆動方法並びにシフトレジスタ回路、論理演算回路、半導体装置
US8072834B2 (en) * 2005-08-25 2011-12-06 Cypress Semiconductor Corporation Line driver circuit and method with standby mode of operation

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3644904A (en) * 1969-11-12 1972-02-22 Gen Instrument Corp Chip select circuit for multichip random access memory
US3810124A (en) * 1972-06-30 1974-05-07 Ibm Memory accessing system
JPS5321984B2 (US06724976-20040420-M00002.png) * 1973-07-13 1978-07-06

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3037130A1 (de) * 1979-10-04 1981-04-09 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Halbleiter-speicherschaltung und adressenbezeichnungsschaltung dafuer
US4447895A (en) * 1979-10-04 1984-05-08 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor memory device
DE3142557A1 (de) * 1980-10-29 1982-08-12 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Integrierte halbleiterschaltungsanordnung
US4490628A (en) * 1980-10-29 1984-12-25 Tokyo Shibaura Denki Kabushiki Kaisha MOS Decoder selection circuit having a barrier transistor whose non-conduction period is unaffected by substrate potential disturbances

Also Published As

Publication number Publication date
FR2344092A1 (fr) 1977-10-07
US4074237A (en) 1978-02-14
JPS5718270B2 (US06724976-20040420-M00002.png) 1982-04-15
JPS52108741A (en) 1977-09-12
IT1118018B (it) 1986-02-24
CA1097814A (en) 1981-03-17
FR2344092B1 (US06724976-20040420-M00002.png) 1979-09-28

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee