DE2704471C2 - Verfahren zur Isolation von Halbleitergebieten - Google Patents

Verfahren zur Isolation von Halbleitergebieten

Info

Publication number
DE2704471C2
DE2704471C2 DE2704471A DE2704471A DE2704471C2 DE 2704471 C2 DE2704471 C2 DE 2704471C2 DE 2704471 A DE2704471 A DE 2704471A DE 2704471 A DE2704471 A DE 2704471A DE 2704471 C2 DE2704471 C2 DE 2704471C2
Authority
DE
Germany
Prior art keywords
layer
semiconductor
conductivity type
substrate
epitaxial
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2704471A
Other languages
German (de)
English (en)
Other versions
DE2704471A1 (de
Inventor
Michel De Caen Brebisson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE2704471A1 publication Critical patent/DE2704471A1/de
Application granted granted Critical
Publication of DE2704471C2 publication Critical patent/DE2704471C2/de
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE2704471A 1976-02-16 1977-02-03 Verfahren zur Isolation von Halbleitergebieten Expired DE2704471C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7604169A FR2341201A1 (fr) 1976-02-16 1976-02-16 Procede d'isolement entre regions d'un dispositif semiconducteur et dispositif ainsi obtenu

Publications (2)

Publication Number Publication Date
DE2704471A1 DE2704471A1 (de) 1977-08-18
DE2704471C2 true DE2704471C2 (de) 1983-08-11

Family

ID=9169154

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2704471A Expired DE2704471C2 (de) 1976-02-16 1977-02-03 Verfahren zur Isolation von Halbleitergebieten

Country Status (9)

Country Link
US (1) US4113513A (enExample)
JP (1) JPS5299767A (enExample)
AU (1) AU505245B2 (enExample)
CA (1) CA1075374A (enExample)
DE (1) DE2704471C2 (enExample)
FR (1) FR2341201A1 (enExample)
GB (1) GB1572854A (enExample)
IT (1) IT1076585B (enExample)
NL (1) NL176622C (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4247862B1 (en) * 1977-08-26 1995-12-26 Intel Corp Ionzation resistant mos structure
JPS56150135A (en) * 1980-01-18 1981-11-20 British Steel Corp Binary steel
US4362574A (en) * 1980-07-09 1982-12-07 Raytheon Company Integrated circuit and manufacturing method
US4381956A (en) * 1981-04-06 1983-05-03 Motorola, Inc. Self-aligned buried channel fabrication process
US9941353B2 (en) * 2016-05-20 2018-04-10 Newport Fab, Llc Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3386865A (en) * 1965-05-10 1968-06-04 Ibm Process of making planar semiconductor devices isolated by encapsulating oxide filled channels
NL7010208A (enExample) * 1966-10-05 1972-01-12 Philips Nv
JPS4836598B1 (enExample) * 1969-09-05 1973-11-06
NL169121C (nl) * 1970-07-10 1982-06-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon.
US3748187A (en) * 1971-08-03 1973-07-24 Hughes Aircraft Co Self-registered doped layer for preventing field inversion in mis circuits
JPS5228550B2 (enExample) * 1972-10-04 1977-07-27
US3886000A (en) * 1973-11-05 1975-05-27 Ibm Method for controlling dielectric isolation of a semiconductor device
JPS5546059B2 (enExample) * 1973-12-22 1980-11-21
US4023195A (en) * 1974-10-23 1977-05-10 Smc Microsystems Corporation MOS field-effect transistor structure with mesa-like contact and gate areas and selectively deeper junctions
US4011105A (en) * 1975-09-15 1977-03-08 Mos Technology, Inc. Field inversion control for n-channel device integrated circuits

Also Published As

Publication number Publication date
NL7701511A (nl) 1977-08-18
GB1572854A (en) 1980-08-06
US4113513A (en) 1978-09-12
AU2224177A (en) 1978-08-24
FR2341201B1 (enExample) 1980-05-09
NL176622C (nl) 1985-05-01
NL176622B (nl) 1984-12-03
IT1076585B (it) 1985-04-27
AU505245B2 (en) 1979-11-15
DE2704471A1 (de) 1977-08-18
CA1075374A (en) 1980-04-08
JPS5299767A (en) 1977-08-22
FR2341201A1 (fr) 1977-09-09
JPS5439708B2 (enExample) 1979-11-29

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Legal Events

Date Code Title Description
OD Request for examination
8126 Change of the secondary classification

Ipc: H01L 21/76

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee