DE2612059A1 - Verfahren und vorrichtung zum befehlsabruf und zur befehlsausfuehrung in einem universalrechner - Google Patents

Verfahren und vorrichtung zum befehlsabruf und zur befehlsausfuehrung in einem universalrechner

Info

Publication number
DE2612059A1
DE2612059A1 DE19762612059 DE2612059A DE2612059A1 DE 2612059 A1 DE2612059 A1 DE 2612059A1 DE 19762612059 DE19762612059 DE 19762612059 DE 2612059 A DE2612059 A DE 2612059A DE 2612059 A1 DE2612059 A1 DE 2612059A1
Authority
DE
Germany
Prior art keywords
register
command
address
instruction
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19762612059
Other languages
German (de)
English (en)
Inventor
Garvin W Patterson
Marion G Porter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Original Assignee
Honeywell Information Systems Italia SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA filed Critical Honeywell Information Systems Italia SpA
Publication of DE2612059A1 publication Critical patent/DE2612059A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE19762612059 1975-03-26 1976-03-22 Verfahren und vorrichtung zum befehlsabruf und zur befehlsausfuehrung in einem universalrechner Withdrawn DE2612059A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US56227275A 1975-03-26 1975-03-26

Publications (1)

Publication Number Publication Date
DE2612059A1 true DE2612059A1 (de) 1976-10-14

Family

ID=24245558

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19762612059 Withdrawn DE2612059A1 (de) 1975-03-26 1976-03-22 Verfahren und vorrichtung zum befehlsabruf und zur befehlsausfuehrung in einem universalrechner

Country Status (6)

Country Link
US (1) US4110822A (enExample)
JP (1) JPS51132731A (enExample)
CA (1) CA1059639A (enExample)
DE (1) DE2612059A1 (enExample)
FR (1) FR2305786A1 (enExample)
GB (1) GB1547387A (enExample)

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US4493020A (en) * 1980-05-06 1985-01-08 Burroughs Corporation Microprogrammed digital data processor employing microinstruction tasking and dynamic register allocation
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US4439827A (en) * 1981-12-28 1984-03-27 Raytheon Company Dual fetch microsequencer
US4477872A (en) * 1982-01-15 1984-10-16 International Business Machines Corporation Decode history table for conditional branch instructions
JPS58146941A (ja) * 1982-02-26 1983-09-01 Hitachi Ltd マイクロプログラム制御デ−タ処理装置
US4454589A (en) * 1982-03-12 1984-06-12 The Unite States of America as represented by the Secretary of the Air Force Programmable arithmetic logic unit
JPS592143A (ja) * 1982-06-29 1984-01-07 Hitachi Ltd 情報処理装置
EP0150177A1 (en) * 1983-07-11 1985-08-07 Prime Computer, Inc. Data processing system
JPH061441B2 (ja) * 1983-09-12 1994-01-05 モトロ−ラ・インコ−ポレ−テツド 先取り確認装置
JPS60107141A (ja) * 1983-11-16 1985-06-12 Fujitsu Ltd プランチ制御方式
US4562537A (en) * 1984-04-13 1985-12-31 Texas Instruments Incorporated High speed processor
US4670835A (en) * 1984-10-19 1987-06-02 Honeywell Information Systems Inc. Distributed control store word architecture
JPH0754461B2 (ja) * 1985-02-08 1995-06-07 株式会社日立製作所 情報処理装置
US5062036A (en) * 1985-06-10 1991-10-29 Wang Laboratories, Inc. Instruction prefetcher
US4761731A (en) * 1985-08-14 1988-08-02 Control Data Corporation Look-ahead instruction fetch control for a cache memory
JPS6280743A (ja) * 1985-10-01 1987-04-14 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション アドレス変換例外処理方法
JPH0727462B2 (ja) * 1985-10-11 1995-03-29 株式会社日立製作所 データ処理装置におけるページフォールト実行再開方法
US4709324A (en) * 1985-11-27 1987-11-24 Motorola, Inc. Data processor control unit having an interrupt service using instruction prefetch redirection
JPS6398737A (ja) * 1986-10-15 1988-04-30 Mitsubishi Electric Corp デ−タ処理装置
US4888689A (en) * 1986-10-17 1989-12-19 Amdahl Corporation Apparatus and method for improving cache access throughput in pipelined processors
US5086498A (en) * 1987-01-23 1992-02-04 Hitachi, Ltd. Parallel computer with asynchronous communication facility
US5179688A (en) * 1987-06-30 1993-01-12 Tandem Computers Incorporated Queue system with uninterrupted transfer of data through intermediate locations to selected queue location
US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries
JP2810043B2 (ja) * 1987-11-13 1998-10-15 株式会社日立製作所 データ処理装置
US5247628A (en) * 1987-11-30 1993-09-21 International Business Machines Corporation Parallel processor instruction dispatch apparatus with interrupt handler
US5179674A (en) * 1988-07-25 1993-01-12 Digital Equipment Corporation Method and apparatus for predicting valid performance of virtual-address to physical-address translations
US4914584A (en) * 1988-10-17 1990-04-03 Gibson Glenn A Rules and apparatus for an intermediate code memory that buffers code segments
US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture
US5333291A (en) * 1991-06-14 1994-07-26 International Business Machines Corporation Stride enhancer for high speed memory accesses with line fetching mode and normal mode employing boundary crossing determination
US5608886A (en) * 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
US5524220A (en) * 1994-08-31 1996-06-04 Vlsi Technology, Inc. Memory subsystems having look-ahead instruction prefetch buffers and intelligent posted write buffers for increasing the throughput of digital computer systems
US7149878B1 (en) 2000-10-30 2006-12-12 Mips Technologies, Inc. Changing instruction set architecture mode by comparison of current instruction execution address with boundary address register values
US7711926B2 (en) * 2001-04-18 2010-05-04 Mips Technologies, Inc. Mapping system and method for instruction set processing
US6826681B2 (en) * 2001-06-18 2004-11-30 Mips Technologies, Inc. Instruction specified register value saving in allocated caller stack or not yet allocated callee stack
US7107439B2 (en) * 2001-08-10 2006-09-12 Mips Technologies, Inc. System and method of controlling software decompression through exceptions
US7552261B2 (en) * 2001-10-12 2009-06-23 Mips Technologies, Inc. Configurable prioritization of core generated interrupts
US7487339B2 (en) * 2001-10-12 2009-02-03 Mips Technologies, Inc. Method and apparatus for binding shadow registers to vectored interrupts
US6970985B2 (en) 2002-07-09 2005-11-29 Bluerisc Inc. Statically speculative memory accessing
US20050114850A1 (en) 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US7996671B2 (en) 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
US20080154379A1 (en) * 2006-12-22 2008-06-26 Musculoskeletal Transplant Foundation Interbody fusion hybrid graft
CA3006039C (en) * 2015-11-30 2026-04-07 Hubbell Incorporated Interrupt exception window protocol on a data communication bus and methods and apparatuses for using same

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US3401376A (en) * 1965-11-26 1968-09-10 Burroughs Corp Central processor
GB1226125A (enExample) * 1967-07-14 1971-03-24
US3573854A (en) * 1968-12-04 1971-04-06 Texas Instruments Inc Look-ahead control for operation of program loops
US3983541A (en) * 1969-05-19 1976-09-28 Burroughs Corporation Polymorphic programmable units employing plural levels of phased sub-instruction sets
JPS514381B1 (enExample) * 1969-11-24 1976-02-10
US3609700A (en) * 1970-02-24 1971-09-28 Burroughs Corp Data processing system having an improved fetch overlap feature
US3764988A (en) * 1971-03-01 1973-10-09 Hitachi Ltd Instruction processing device using advanced control system
BE789583A (fr) * 1971-10-01 1973-02-01 Sanders Associates Inc Appareil de controle de programme pour machine de traitement del'information
US3840861A (en) * 1972-10-30 1974-10-08 Amdahl Corp Data processing system having an instruction pipeline for concurrently processing a plurality of instructions
US3811114A (en) * 1973-01-11 1974-05-14 Honeywell Inf Systems Data processing system having an improved overlap instruction fetch and instruction execution feature
JPS5247976B2 (enExample) * 1973-03-16 1977-12-06
GB1426749A (en) * 1973-06-05 1976-03-03 Burroughs Corp Micro programme data processor having parallel instruction flow streams for plural level of subinstruction sets
IT993428B (it) * 1973-09-26 1975-09-30 Honeywell Inf Systems Unita di controllo di calcolatore microprogrammato con microprogram mi residenti in memoria e sovrap posizioni delle fasi interpretati ve di una microistruzione con la fase esecutiva della precedente microistruzione
US3875391A (en) * 1973-11-02 1975-04-01 Raytheon Co Pipeline signal processor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM-Journal, Januar 1967, S. 8-24 *

Also Published As

Publication number Publication date
US4110822A (en) 1978-08-29
FR2305786B1 (enExample) 1979-05-18
JPS51132731A (en) 1976-11-18
FR2305786A1 (fr) 1976-10-22
GB1547387A (en) 1979-06-20
CA1059639A (en) 1979-07-31

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8139 Disposal/non-payment of the annual fee