DE2558925C2 - Verfahren zur Herstellung einer integrierten Injektions-Schaltungsanordnung - Google Patents

Verfahren zur Herstellung einer integrierten Injektions-Schaltungsanordnung

Info

Publication number
DE2558925C2
DE2558925C2 DE2558925A DE2558925A DE2558925C2 DE 2558925 C2 DE2558925 C2 DE 2558925C2 DE 2558925 A DE2558925 A DE 2558925A DE 2558925 A DE2558925 A DE 2558925A DE 2558925 C2 DE2558925 C2 DE 2558925C2
Authority
DE
Germany
Prior art keywords
conductive
zone
layer
type
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2558925A
Other languages
German (de)
English (en)
Other versions
DE2558925A1 (de
Inventor
Shintaro Ito
Masanori Nakai
Junichi Nakamura
Yoshio Yokohama Nishi
Satoshi Shinozaki
Yukuya Tokumaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP14879574A external-priority patent/JPS5513584B2/ja
Priority claimed from JP50001913A external-priority patent/JPS5182583A/ja
Priority claimed from JP14879674A external-priority patent/JPS5426471B2/ja
Priority claimed from JP14879774A external-priority patent/JPS5415396B2/ja
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of DE2558925A1 publication Critical patent/DE2558925A1/de
Application granted granted Critical
Publication of DE2558925C2 publication Critical patent/DE2558925C2/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials

Landscapes

  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
DE2558925A 1974-12-27 1975-12-29 Verfahren zur Herstellung einer integrierten Injektions-Schaltungsanordnung Expired DE2558925C2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP14879574A JPS5513584B2 (enExample) 1974-12-27 1974-12-27
JP50001913A JPS5182583A (en) 1974-12-27 1974-12-27 Handotaisochino seizohoho
JP14879674A JPS5426471B2 (enExample) 1974-12-27 1974-12-27
JP14879774A JPS5415396B2 (enExample) 1974-12-27 1974-12-27

Publications (2)

Publication Number Publication Date
DE2558925A1 DE2558925A1 (de) 1976-07-08
DE2558925C2 true DE2558925C2 (de) 1985-10-31

Family

ID=27453504

Family Applications (2)

Application Number Title Priority Date Filing Date
DE2558925A Expired DE2558925C2 (de) 1974-12-27 1975-12-29 Verfahren zur Herstellung einer integrierten Injektions-Schaltungsanordnung
DE2560576A Expired DE2560576C2 (de) 1974-12-27 1975-12-29 Verfahren zum Herstellen einer integrierten Injektions-Schaltungsanordnung

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE2560576A Expired DE2560576C2 (de) 1974-12-27 1975-12-29 Verfahren zum Herstellen einer integrierten Injektions-Schaltungsanordnung

Country Status (4)

Country Link
US (1) US4058419A (enExample)
DE (2) DE2558925C2 (enExample)
FR (1) FR2334204A1 (enExample)
GB (1) GB1528027A (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5317081A (en) * 1976-07-30 1978-02-16 Sharp Corp Production of i2l device
DE2652103C2 (de) * 1976-11-16 1982-10-28 Ibm Deutschland Gmbh, 7000 Stuttgart Integrierte Halbleiteranordnung für ein logisches Schaltungskonzept und Verfahren zu ihrer Herstellung
US4180827A (en) * 1977-08-31 1979-12-25 International Business Machines Corporation NPN/PNP Fabrication process with improved alignment
CA1116309A (en) * 1977-11-30 1982-01-12 David L. Bergeron Structure and process for optimizing the characteristics of i.sup.2l devices
US4168999A (en) * 1978-12-26 1979-09-25 Fairchild Camera And Instrument Corporation Method for forming oxide isolated integrated injection logic semiconductor structures having minimal encroachment utilizing special masking techniques
US4317690A (en) * 1980-06-18 1982-03-02 Signetics Corporation Self-aligned double polysilicon MOS fabrication
US4446611A (en) * 1980-06-26 1984-05-08 International Business Machines Corporation Method of making a saturation-limited bipolar transistor device
DE3136731A1 (de) * 1981-09-16 1983-03-31 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen einer halbleiteranordnung
US5759902A (en) * 1986-09-26 1998-06-02 Analog Devices, Incorporated Method of making an integrated circuit with complementary junction-isolated bipolar transistors
CN102299070A (zh) * 2010-06-22 2011-12-28 无锡华润上华半导体有限公司 横向pnp晶体管的制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3328214A (en) * 1963-04-22 1967-06-27 Siliconix Inc Process for manufacturing horizontal transistor structure
US3472710A (en) * 1967-04-20 1969-10-14 Teledyne Inc Method of forming a field effect transistor
US3489622A (en) * 1967-05-18 1970-01-13 Ibm Method of making high frequency transistors
US3560278A (en) * 1968-11-29 1971-02-02 Motorola Inc Alignment process for fabricating semiconductor devices
NL7010211A (enExample) * 1969-07-12 1971-01-14
DE2262297C2 (de) * 1972-12-20 1985-11-28 Ibm Deutschland Gmbh, 7000 Stuttgart Monolithisch integrierbare, logisch verknüpfbare Halbleiterschaltungsanordnung mit I↑2↑L-Aufbau
US3873989A (en) * 1973-05-07 1975-03-25 Fairchild Camera Instr Co Double-diffused, lateral transistor structure
US3919005A (en) * 1973-05-07 1975-11-11 Fairchild Camera Instr Co Method for fabricating double-diffused, lateral transistor
GB1507061A (en) * 1974-03-26 1978-04-12 Signetics Corp Semiconductors
US3982266A (en) * 1974-12-09 1976-09-21 Texas Instruments Incorporated Integrated injection logic having high inverse current gain

Also Published As

Publication number Publication date
FR2334204A1 (fr) 1977-07-01
DE2558925A1 (de) 1976-07-08
DE2560576C2 (de) 1985-10-31
US4058419A (en) 1977-11-15
FR2334204B1 (enExample) 1978-05-26
GB1528027A (en) 1978-10-11

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D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KABUSHIKI KAISHA TOSHIBA, KAWASAKI, KANAGAWA, JP