DE2555155A1 - Dielektrisch isolierte unterlage fuer integrierte halbleiterschaltungen und verfahren zu ihrer herstellung - Google Patents

Dielektrisch isolierte unterlage fuer integrierte halbleiterschaltungen und verfahren zu ihrer herstellung

Info

Publication number
DE2555155A1
DE2555155A1 DE19752555155 DE2555155A DE2555155A1 DE 2555155 A1 DE2555155 A1 DE 2555155A1 DE 19752555155 DE19752555155 DE 19752555155 DE 2555155 A DE2555155 A DE 2555155A DE 2555155 A1 DE2555155 A1 DE 2555155A1
Authority
DE
Germany
Prior art keywords
silicon
polycrystalline
layers
layer
polycrystalline silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19752555155
Other languages
German (de)
English (en)
Other versions
DE2555155C2 (en, 2012
Inventor
Akio Mimura
Takaya Suzuki
Seturoo Yaguu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Publication of DE2555155A1 publication Critical patent/DE2555155A1/de
Application granted granted Critical
Publication of DE2555155C2 publication Critical patent/DE2555155C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/097—Lattice strain and defects
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Recrystallisation Techniques (AREA)
DE19752555155 1974-12-11 1975-12-08 Dielektrisch isolierte unterlage fuer integrierte halbleiterschaltungen und verfahren zu ihrer herstellung Granted DE2555155A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14155574A JPS5718341B2 (en, 2012) 1974-12-11 1974-12-11

Publications (2)

Publication Number Publication Date
DE2555155A1 true DE2555155A1 (de) 1976-06-16
DE2555155C2 DE2555155C2 (en, 2012) 1989-06-22

Family

ID=15294680

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752555155 Granted DE2555155A1 (de) 1974-12-11 1975-12-08 Dielektrisch isolierte unterlage fuer integrierte halbleiterschaltungen und verfahren zu ihrer herstellung

Country Status (4)

Country Link
US (1) US4079506A (en, 2012)
JP (1) JPS5718341B2 (en, 2012)
CA (1) CA1039414A (en, 2012)
DE (1) DE2555155A1 (en, 2012)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4173674A (en) * 1975-05-12 1979-11-06 Hitachi, Ltd. Dielectric insulator separated substrate for semiconductor integrated circuits
US4242697A (en) * 1979-03-14 1980-12-30 Bell Telephone Laboratories, Incorporated Dielectrically isolated high voltage semiconductor devices
JPS55138229A (en) * 1979-04-13 1980-10-28 Hitachi Ltd Manufacture of dielectric material for insulation- separation substrate
US4278705A (en) * 1979-11-08 1981-07-14 Bell Telephone Laboratories, Incorporated Sequentially annealed oxidation of silicon to fill trenches with silicon dioxide
US4411060A (en) * 1981-07-06 1983-10-25 Western Electric Co., Inc. Method of manufacturing dielectrically-isolated single-crystal semiconductor substrates
US4879585A (en) * 1984-03-31 1989-11-07 Kabushiki Kaisha Toshiba Semiconductor device
US4631804A (en) * 1984-12-10 1986-12-30 At&T Bell Laboratories Technique for reducing substrate warpage springback using a polysilicon subsurface strained layer
US4581814A (en) * 1984-12-13 1986-04-15 At&T Bell Laboratories Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation
US4742020A (en) * 1985-02-01 1988-05-03 American Telephone And Telegraph Company, At&T Bell Laboratories Multilayering process for stress accommodation in deposited polysilicon
US4631803A (en) * 1985-02-14 1986-12-30 Texas Instruments Incorporated Method of fabricating defect free trench isolation devices
US4983226A (en) * 1985-02-14 1991-01-08 Texas Instruments, Incorporated Defect free trench isolation devices and method of fabrication
US4606936A (en) * 1985-04-12 1986-08-19 Harris Corporation Stress free dielectric isolation technology
JPS62224687A (ja) * 1986-03-25 1987-10-02 Anelva Corp エツチング方法
JPS63182836A (ja) * 1987-01-24 1988-07-28 Matsushita Electric Works Ltd 絶縁層分離基板の製法
US4830984A (en) * 1987-08-19 1989-05-16 Texas Instruments Incorporated Method for heteroepitaxial growth using tensioning layer on rear substrate surface
JPH02102569A (ja) * 1988-10-12 1990-04-16 Nippon Telegr & Teleph Corp <Ntt> 半導体装置
US5023200A (en) * 1988-11-22 1991-06-11 The United States Of America As Represented By The United States Department Of Energy Formation of multiple levels of porous silicon for buried insulators and conductors in silicon device technologies
GB9014491D0 (en) * 1990-06-29 1990-08-22 Digital Equipment Int Mounting silicon chips
US5562770A (en) * 1994-11-22 1996-10-08 International Business Machines Corporation Semiconductor manufacturing process for low dislocation defects
DE10246949B4 (de) * 2002-10-08 2012-06-28 X-Fab Semiconductor Foundries Ag Verbesserte Trench-Isolation und Herstellungsverfahren

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1509644A (fr) * 1966-01-31 1968-01-12 Centre Electron Horloger Procédé de fabrication d'un circuit intégré
DE1298189B (de) * 1964-12-14 1969-06-26 Motorola Inc Verfahren zum Herstellen von isolierten Bereichen in einer integrierten Halbleiter-Schaltung
DE2050474A1 (de) * 1969-10-17 1971-04-22 Motorola Inc Zusammengesetzte Halbleiterscheibe mit gegeneinander isolierten Inselberei chen und Verfahren zur Herstellung derar tiger Halbleiterscheiben
DE2458680A1 (de) * 1973-12-14 1975-06-26 Hitachi Ltd Verfahren zur herstellung von dielektrisch isolierten substraten fuer monolithische integrierte halbleiterschaltkreise

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3331716A (en) * 1962-06-04 1967-07-18 Philips Corp Method of manufacturing a semiconductor device by vapor-deposition
US3829889A (en) * 1963-12-16 1974-08-13 Signetics Corp Semiconductor structure
US3423255A (en) * 1965-03-31 1969-01-21 Westinghouse Electric Corp Semiconductor integrated circuits and method of making the same
US3411200A (en) * 1965-04-14 1968-11-19 Westinghouse Electric Corp Fabrication of semiconductor integrated circuits
US3368113A (en) * 1965-06-28 1968-02-06 Westinghouse Electric Corp Integrated circuit structures, and method of making same, including a dielectric medium for internal isolation
GB1224801A (en) * 1967-03-01 1971-03-10 Sony Corp Methods of manufacturing semiconductor devices
US3574007A (en) * 1967-07-19 1971-04-06 Frances Hugle Method of manufacturing improved mis transistor arrays
JPS4715928U (en, 2012) * 1971-03-24 1972-10-24

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1298189B (de) * 1964-12-14 1969-06-26 Motorola Inc Verfahren zum Herstellen von isolierten Bereichen in einer integrierten Halbleiter-Schaltung
FR1509644A (fr) * 1966-01-31 1968-01-12 Centre Electron Horloger Procédé de fabrication d'un circuit intégré
DE2050474A1 (de) * 1969-10-17 1971-04-22 Motorola Inc Zusammengesetzte Halbleiterscheibe mit gegeneinander isolierten Inselberei chen und Verfahren zur Herstellung derar tiger Halbleiterscheiben
DE2458680A1 (de) * 1973-12-14 1975-06-26 Hitachi Ltd Verfahren zur herstellung von dielektrisch isolierten substraten fuer monolithische integrierte halbleiterschaltkreise

Also Published As

Publication number Publication date
JPS5718341B2 (en, 2012) 1982-04-16
DE2555155C2 (en, 2012) 1989-06-22
US4079506A (en) 1978-03-21
CA1039414A (en) 1978-09-26
JPS5168189A (en, 2012) 1976-06-12

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