DE2555155A1 - DIELECTRICALLY INSULATED BASE FOR INTEGRATED SEMICONDUCTOR CIRCUITS AND THE PROCESS FOR THEIR PRODUCTION - Google Patents

Description

Dielectric insulated pad for integrated semiconductor circuits and processes
for their manufacture

The invention relates to a dielectrically insulated support for integrated semiconductor circuits and a method for their production. Included
it is in particular about dielectrically insulated bases for integrated semiconductors with a plurality of monocrystalline silicon islands in which circuit components are formed that are dielectrically isolated from one another and from the base for the purpose of forming monolithic integrated
Semiconductor circuits are isolated.

The dielectrically insulated base may comprise a large number of single-crystal silicon islands, which is fixed to a polyicrystalline silicon carrier layer via a dielectric insulating film made of silicon oxide are connected. Such is the mechanical cohesion between the individual monocrystalline silicon islands and between the polycrystalline silicon substrate

8I-AI205-02-TH (7)

609825/0727

rail and the individual monocrystalline silicon islands secured, and these elements are electrically isolated from each other.

Such Scnaltungbauelemente such. B. transistors, Diodes, resistors and capacitors, are in the numerous single crystal silicon islands by diffusion technology introduced and among each other to form a monolithic integrated semiconductor circuit tied together.

A typical known method for the production of such a dielectrically insulated base is described with reference to the Fig. la-ld are explained.

One surface of a single crystal silicon wafer 1 as disclosed in Pig. 1a, is provided with spaced-apart grooves 2 for selective etching and then coated with a SiOp film 3 for insulation purposes, as illustrated in FIG. 1b. A polycrystalline silicon layer 4 is deposited on the SiOp film 3 by the vapor phase reaction of silicon chloride, as FIG. 1c shows. On the surface of this polycrystalline layer 4, one can see, corresponding to the grooves 2, small depressions 5 To generate island areas 6, which are separated from one another by the SiO ₂ -FiIm 3, as can be seen in Fig. Id. By diffusing desired impurities into the island areas 6 according to the known selective

609825/0727

The circuit components can then be produced using a diffusion method.

Jedo.cn results from the above-described known method for producing the dielectrically insulated Underlay the difficult problem that the underlay 7 after the step of depositing the polycrystalline Layer 4 according to FIG. 1c has a curvature. This problem can be caused by (1) the difference in thermal expansion coefficients between the single crystal Silicon wafer and the polycrystalline silicon layer and (2) the contraction due to recrystallization of the polycrystalline layer itself during its growth be caused. In particular, the polycrystalline layer tends to take a concave shape. The underlay 7 with curvatures formed in this way prevents the monocrystalline platelet from subsequently grinding and Polishing process is polished uniformly, which results in one to be used for selective diffusion Do not bring the photoresist mask into close contact with the polished surface of the single crystal wafer leaves.

The invention is based on the object of providing a dieelectrically insulated pad for integrated semiconductor circuits with a fine structure and a corresponding Specify manufacturing processes that allow high precision in mass production by lowering Curvature of the substrate is guaranteed, so that both precise grinding and polishing processes as well as a more accurate Have the photo-etching process carried out.

609825/0 7 27

The object of the invention, with which this object is achieved, is initially a dielectrically isolated Base for integrated semiconductor circuits with a plurality of single-crystal silicon islands in which Circuit components are formed, a polycrystalline silicon substrate and one between the monocrystalline Silicon islands and the carrier layer attached, the silicon islands from one another and from the carrier layer insulating silicon oxide film, characterized in that the support layer area consists of an alternating Layer sequence consists of 3 to 12 polycrystalline silicon layers and interposed silicon oxide layers.

In a method for producing such a dielectrically insulated base, in which one in a Main surface of a single crystal silicon wafer forms grooves at intervals on the surface with the Grooves a dielectric film provides on the dielectric film polycrystalline silicon as a support layer The opposite, smooth main surface of the silicon wafer is polished until the grooves face outwards and a plurality of single crystal silicon islands isolated by the dielectric film are formed The object is achieved according to the invention in that one after Providing the dielectric film 3 thereon as a carrier layer area an alternating layer sequence of 3 to 12 polycrystalline silicon layers and interposed ones Deposits silicon oxide layers before polishing the opposite major surface of the single crystal silicon wafer makes.

609825/0727

This takes advantage of the fact that polycrystalline silicon is larger, silicon dioxide, on the other hand has a smaller coefficient of thermal expansion than that of the monocrystalline silicon. Through the alternating layer sequences of polycrystalline silicon layers and silicon dioxide films can therefore be used practically avoid a curvature of the surface.

By adding such oxidizing gases as e.g. B. carbon dioxide gas, oxygen and water vapor, in a certain time interval to a reaction gas that is formed when a silicon-chlorine compound, z. B. trichlorosilane (SiHCl-,), reacts with hydrogen under vapor phase reduction reaction for the deposition of polycrystalline »silicon, the multilayer structure can be easily and continuously, ie without removing the single crystalline platelet from the reaction furnace in the course of the coating reaction. When the substrate portion is formed with the multilayer structure according to essentially the above-described technique, the degree and the direction of the curvature can be controlled by appropriately selecting the number of polycrystalline layers so that it is possible to produce a substrate suitable for practical use Purposes can be viewed essentially as curvature-free. In particular, the pad, when the number of polycrystalline layers in the range of 3 - 12 is selected to be practically free from the formation of a curvature.

The invention is explained in more detail with reference to the exemplary embodiment illustrated in the drawing; in this demonstrate:

60982B / 0727

Pig. la to ld the sectional views already explained to illustrate the individual process steps of a known method for producing a dielectrically insulated base;

2a to 2d are sectional views for illustration the individual process steps of a process for producing a dielectrically insulated Pad according to the invention;

3 is a graphical representation of experimental results to illustrate the relationship between the number of polycrystalline silicon layers of a multi-layer carrier sheet.
the document;

gen carrier layer area and the curvature

Fig. 4 is a graphical representation for illustrative purposes the relationship between the thickness of a polycrystalline support layer region with a single-layer structure and the curvature of the Document;

Fig. 5 is a graph for explaining how the number of layers for a multilayer structure is to be determined, who is to generate a * document with lower Curvature, in particular with a radius of curvature of more than about 10 m;

609825/0727

Pig. 6 is a sectional view of another embodiment the invention; and

Fig. 7 is a sectional view of a further embodiment of the invention.

A monocrystalline silicon wafer 10 of the N-type with a thickness of 300-100 μm and a (10Q) surface orientation with ground and polished parallel surfaces, as shown in FIG Grooves 11 formed at mutual intervals, as shown in Fig. 2b. The single-crystalline wafer 10 provided with the spaced-apart Jsuten 11 is placed in a reaction furnace, as it is used for conventional epitaxial growth processes, and at a high temperature of 1100 to 125O ° C in the atmosphere of a flowing gas mixture, the trichlorosilane (SiHGl,), Contains hydrogen and carbon dioxide gas (CO ₂ ), coated with silicon oxide 12 to a thickness of 1.5 µm. This is followed by the deposition of a first polycrystalline silicon layer 13a of about 45 μm thickness when a gas mixture containing trichlorosilane and hydrogen then flows, whereas the carbon dioxide gas flow is interrupted, the reaction temperature being maintained. Then, by again admitting carbon dioxide gas into the reaction system with continued supply of trichlorosilane and hydrogen, a silicon oxide film 14a of about 0.3 to 2 µm in thickness is formed on the first polycrystalline layer 13a. In this way, silicon oxide films 14a

609825/0727

to 14m and polycrystalline silicon layers 13a to 13n are alternately stacked with the proviso that the flow rate of hydrogen gas and carbon dioxide gas for mixing with trichlorosilane is regulated according to the reaction steps desired in each case. The reaction temperature is maintained unchanged. Thus, after the silicon oxide film I ¹ Ja is formed, the introduction of carbon dioxide gas into the reaction system is interrupted again and the flow rates of trichlorosilane and hydrogen are reduced to the value for the formation of the polycrystalline silicon layer 13a, so that a second polycrystalline silicon layer 13b of about 45 to form thickness. By repeating these process steps, a third, fourth and fifth polycrystalline silicon layer each approximately 45 μm thick and thus alternately silicon oxide films each 0.3-2 μm thick are formed, so that a carrier area 15 with a multilayer structure totaling approximately 230 to obtain thickness consisting of polycrystalline silicon layers and silicon oxide films.

When generating the carrier area 15 with the multilayer structure, other silicon-chlorine compounds than trichlorosilane, such as. B. silicon tetrachloride (SiCl ₁₁ ) or dichlorosilane (SiH ₂ Cl ₂ ) or monosilane (SiH _1. ) Can be used as the silicon source, and you can also use other oxidizing gases, such as. Use water vapor, oxygen and nitrogen dioxide in place of the carbon dioxide gas. This technique is illustrated in U.S. Patent Application 531,167 dated Dec. 9, 1974.

609825/0727

A base 16 with the multi-layer carrier area 15 'which in this way is five times polycrystalline Layer has received, gives a radius of curvature in the range of 10 to 100 m and thus has a Significantly reduced curvature compared to a 3 to 5 m radius of curvature of a pad with the known single-layer polycrystalline carrier area 4 according to FIG. 1, if you have documents with a total of same thickness compares.

The size and the direction of the curvature of the base 16 with the multilayer carrier area 15 can be determined control by the number of polycrystalline silicon layers.

Pig. Fig. 3 shows an example of test results showing the relationship between the multilayer structure and the curvature of the substrate. The size of the curvature is given on the one hand as the maximum deflection H and on the other hand as the radius of curvature for the case that the base has a diameter of 50 mm, with the plus sign indicating a concave curvature of the carrier area (and, accordingly, a convex curvature of the single-crystalline plate) and the minus sign being a corresponds to the convex curvature of the carrier area. The curve oil gives the measured values for a carrier area with a total thickness of 210-260 μm and the curve β the measured values for a carrier area with a total thickness of 430 to 480 μm. As the number of polycrystalline silicon layers increases, the direction of curvature reverses so that the polycrystalline silicon substrate area begins,

609825/0727

- ίο -

take the form of a convex surface. In this way, the carrier area with the multilayer structure the size and the direction of curvature of the substrate as desired by the number of polycrystalline Control layers with very good reproducibility. It should be noted that the relationship between the number of the polycrystalline silicon layers and the curvature of the substrate depends on the total thickness of the carrier area. Pig. Fig. 4 shows the measurement-based relationship between the thickness of the polycrystalline support region with a single-layer structure and the curvature of the base. Plus sign values on the ordinate again indicate that the polycrystalline carrier area shows a concave curvature as shown on the left in FIG. 3. The thicker the polycrystalline The greater the curvature of the substrate, the greater the carrier area.

It is derived from Figs. 3 and 4 and other experimental results that when a polycrystalline silicon layer and silicon oxide films, polycrystalline multilayer support area of about 200,500 .um thickness on a 300 - 100 .um thick monocrystalline Silicon platelets with (100) surface orientation formed at growth temperatures of 1100 to 125O ° C becomes the relationship between the curvature of the substrate and the number of polycrystalline silicon layers approximated by the following empirically determined formula

H eg A η + B ^

can be obtained where H is the maximum allowable

609825/0727

- ii -

Bend deflection in .um for a base with a Diameter of 50 mm, η (positive integer) the number of polycrystalline silicon layers and A and B constants mean.

In general, the curvature of the substrate with the multilayer structure depends to a large extent on the number of polycrystalline silicon layers and their thickness, as described. Other parameters which have an influence on the magnitude of the curvature are the thickness of the monocrystalline wafer, its surface orientation, the growth temperature of the polycrystalline silicon layers, their growth rate and the thickness of the silicon oxide films. Among them, the face orientation of the single crystal wafer and the thickness of the silicon oxide films have relatively little influence on the curvature, so that their influence can be almost negligible. It has been verified that such parameters as the thickness of the single crystal wafer, the growth temperature of the polycrystalline silicon layers and the growth rate thereof mainly influence the constant B of the formula (1) but have little influence on the constant A. Experimental results showed that, under the condition that the thickness of the single crystal plate 300-100 to the thickness of the support portion 200-500 to the growth temperature of the polycrystalline silicon layers 1100 to 1250 ⁰ C and the growth rate of 1 to 8, um / min be, values of A = -18 (, um per individual layer) and of B =? 60 - 200 (um) apply »You can see from these test results that

609825/0727

that the number of polycrystalline silicon layers in the multilayer structure under the above conditions preferably 3 - 12 should be around a base if possible small curvature with a radius of curvature greater than 10 m for practical purposes satisfied, as is indicated within the hatched area in FIG.

In the most common manufacturing process for the dielectrically insulated substrate, a single-crystalline platelet with a diameter of Mo - 90 mm and a thickness of 200-400 μm is used as the starting crystal and a polycrystalline silicon layer is left at temperatures of 1100 to 1250 ^° C. and growth rates of 1-8 to grow up to / min. Therefore, the conditions given above to illustrate the invention are satisfactory for practical purposes.

By removing the coated with the carrier area 15 of the multiple-layer structure produced in this way single crystal wafer 10 by means of grinding and mirror polishing up to one by one in Fig. 2c The finished dielectrically insulated base is obtained at the level indicated by the dashed-dotted line 16 with single crystal N island regions 17 · The Base 16 formed with the polycrystalline carrier area 15 is obtained essentially without curvature, so that the aforementioned polishing process can be performed with high uniformity and accuracy as compared with that known procedures can run and so a noticeable

609825/0727

Improvement in product yield is achieved.

In the individual monocrystalline island areas of the dielectrically insulated base produced in this way 16 circuit components such as transistors, Form diodes, resistors and capacitors with high accuracy.

In the known method, according to which the base is formed with the single polycrystalline layer, the polycrystalline silicon layer inevitably has a concave curvature, since this layer has a higher coefficient of thermal expansion of 7.6 * 10 ~ / ⁰ C than that of the monocrystalline silicon wafer of 2, 5 * ^10/0 C. In addition, it can be assumed that a silicon polycrystal undergoes a certain contraction by itself due to the rearrangement of the atoms when it grows through a vapor phase reaction at high temperature. This phenomenon can therefore easily lead to a concave curvature of the polycrystalline layer of the base if the carrier area is produced from a single polycrystalline layer. The radius of such a concave curvature is usually smaller than about 5-7 m and depends on the conditions of the growth of the polycrystalline silicon layer. On the other hand, when the support region 5 takes the form of a multilayer structure composed of a plurality of polycrystalline silicon layers and silicon oxide films according to the present invention, the silicon oxide films act as the cause

6 09825/0 7 27

counteracting the concave curvature of the polycrystalline layer area by compensating the curvature, so that the radius of curvature of the base can easily be increased in a controlled manner up to more than 10 m, whereby the degree of curvature is very largely reduced. This effect of the invention is believed to be due to the fact that the silicon oxide film has a coefficient of thermal expansion far lower than that of the silicon single crystal of 0.5 x 10 ~ / ⁰ G and that when the silicon oxide film is formed, oxygen present in the grain boundaries within the polycrystalline silicon layer Grain boundary area penetrates or diffuses to form an oxidized surface of the grain boundaries or a deposition of silicon oxide, which is effective for expanding the polycrystalline layer or preventing its contraction.

Although the invention so far only relates to the formation of a polycrystalline multilayer support region for supporting the dielectrically insulated support of single-crystal islands has been described, it is on the Production of such a dielectrically insulated base alone is not limited. Obviously that is Invention broadly applied to the manufacture of semiconductor substrates applicable that require a polycrystalline support area. For example, in FIG. 6 as a further exemplary embodiment of the invention, a carrier region 22 for receiving a monocrystalline thin-film silicon layer 21 shown, the carrier area alternating from silicon oxide films 23 and

609825/0 7 27

polycrystalline silicon layers 24 consists. In the end Another embodiment of the invention is shown in Fig. 7, after which a large number of single crystal Silicon wafer is carried by a support region 32 which is made up of alternating silicon oxide films and polycrystalline silicon layers 3 ^.

609825/0727

Claims (5)

- 16 claims f IJ Dielectric insulated pad for integrated Semiconductor circuits comprising a plurality of monocrystalline silicon islands in which circuit components are formed are, a polycrystalline silicon substrate and one between the single crystal silicon islands and attached to the carrier layer, isolating the silicon islands from one another and from the carrier layer Silicon oxide film, characterized, that the carrier layer area (15) consists of an alternating layer sequence of 3 to 12 polycrystalline silicon layers (13a ... 13n) and interposed silicon oxide layers (l4a ... l4m). 2. A method for producing a dielectrically insulated support according to claim 1, in which one main surface of a single crystal silicon wafer forms grooves at intervals on the surface with the grooves provides a dielectric film on which polycrystalline silicon is deposited as a carrier layer, the opposite, smooth main surface of the silicon wafer is polished until the grooves extend outwards and a plurality of single crystal silicon islands isolated by the dielectric film are formed, characterized in that that, after the dielectric film (12) has been provided on this as a carrier layer region (15), an alternating Layer sequence of 3 to 12 polycrystalline 6 0 9 8 2 5/0727 Silicon layers (13a ... 13n) and interposed
Deposits silicon oxide layers (14a ... I ¹ Jm) before the polishing of the opposite main surface of the single-crystal silicon wafer (10) is carried out. 3. The method according to claim 2, characterized in that a single-crystal silicon plate (10) of 300-100 μm in thickness and the carrier layer region (15) in a thickness of 200 to 500 μm by growing the polycrystalline silicon layers
(13a ... 13n) and the silicon oxide films deposited (14a ... L4M) from the vapor phase at temperatures from 1100 to 1250 ⁰ C and at a growth rate of polycrystalline silicon layers of 1 to 8, um / min. 4. The method according to claim 3 »characterized in that that for a base (16) with a diameter of 50 mm, the number η of the polycrystalline silicon layers to be deposited (13a ... 13n) according to the formula H- A · η + B determines where H is the maximum permissible deflection in, um, A is a constant determined by the relationship A = * -18 (.um per individual layer) and B is a
mean constant determined by the relationship B ^ 60 to 200 (.mu.m). 609825/0 7 2? 5. The method according to claim 2 or 3, characterized in that each polycrystalline silicon layer (13a ... 13n) of the carrier layer area (15) with a thickness of about 45 / µm and each silicon oxide film (14a ... l4m) a thickness of 0.3 to 2 .um is deposited. 609825/0727 Read on