GB1224803A - Semiconductor devices - Google Patents
Semiconductor devicesInfo
- Publication number
- GB1224803A GB1224803A GB40776/70A GB4077670A GB1224803A GB 1224803 A GB1224803 A GB 1224803A GB 40776/70 A GB40776/70 A GB 40776/70A GB 4077670 A GB4077670 A GB 4077670A GB 1224803 A GB1224803 A GB 1224803A
- Authority
- GB
- United Kingdom
- Prior art keywords
- semi
- layers
- recess
- conductor
- support
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/115—Orientation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
Abstract
1,224,803. Semi-conductor devices. SONY CORP. 26 Feb., 1968 [1 March, 1967 (5)], No. 40776/70. Divided out of 1,224,801. Heading HlK. The subject-matter of this Specification is entirely contained in Specification 1,224,801 but the claims relate to a semi-conductor device comprising a support having a recess in a surface thereof with two sequentially vapour grown semi-conductor layers in said recess lying parallel to its sides and bottom, with semiconductor material filling the portion of the recess surrounded by the layers. The effective width of at least one of the layers at its exposed cross-section at the support surface is greater than the thickness of the bottom portion of that layer in order to facilitate attachment of an electrode thereto.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1301667 | 1967-03-01 | ||
JP1301467 | 1967-03-01 | ||
JP1301367 | 1967-03-01 | ||
JP1301767 | 1967-03-01 | ||
JP1301567 | 1967-03-01 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1224803A true GB1224803A (en) | 1971-03-10 |
Family
ID=27519466
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB40776/70A Expired GB1224803A (en) | 1967-03-01 | 1968-02-26 | Semiconductor devices |
GB9240/68A Expired GB1224801A (en) | 1967-03-01 | 1968-02-26 | Methods of manufacturing semiconductor devices |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB9240/68A Expired GB1224801A (en) | 1967-03-01 | 1968-02-26 | Methods of manufacturing semiconductor devices |
Country Status (3)
Country | Link |
---|---|
US (1) | US3575731A (en) |
DE (1) | DE1639418A1 (en) |
GB (2) | GB1224803A (en) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5718341B2 (en) * | 1974-12-11 | 1982-04-16 | ||
DE2658304C2 (en) * | 1975-12-24 | 1984-12-20 | Tokyo Shibaura Electric Co., Ltd., Kawasaki, Kanagawa | Semiconductor device |
US4161743A (en) * | 1977-03-28 | 1979-07-17 | Tokyo Shibaura Electric Co., Ltd. | Semiconductor device with silicon carbide-glass-silicon carbide passivating overcoat |
US4104086A (en) * | 1977-08-15 | 1978-08-01 | International Business Machines Corporation | Method for forming isolated regions of silicon utilizing reactive ion etching |
US4636269A (en) * | 1983-11-18 | 1987-01-13 | Motorola Inc. | Epitaxially isolated semiconductor device process utilizing etch and refill technique |
US4804866A (en) * | 1986-03-24 | 1989-02-14 | Matsushita Electric Works, Ltd. | Solid state relay |
US4902641A (en) * | 1987-07-31 | 1990-02-20 | Motorola, Inc. | Process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure |
US4786615A (en) * | 1987-08-31 | 1988-11-22 | Motorola Inc. | Method for improved surface planarity in selective epitaxial silicon |
US4876212A (en) * | 1987-10-01 | 1989-10-24 | Motorola Inc. | Process for fabricating complimentary semiconductor devices having pedestal structures |
JPH067594B2 (en) * | 1987-11-20 | 1994-01-26 | 富士通株式会社 | Method for manufacturing semiconductor substrate |
US5278083A (en) * | 1992-10-16 | 1994-01-11 | Texas Instruments Incorporated | Method for making reliable connections to small features of integrated circuits |
FR2816113A1 (en) * | 2000-10-31 | 2002-05-03 | St Microelectronics Sa | METHOD FOR PRODUCING A DOPED AREA IN SILICON CARBIDE AND APPLICATION TO A SCHOTTKY DIODE |
-
1968
- 1968-02-26 GB GB40776/70A patent/GB1224803A/en not_active Expired
- 1968-02-26 GB GB9240/68A patent/GB1224801A/en not_active Expired
- 1968-02-28 US US708946A patent/US3575731A/en not_active Expired - Lifetime
- 1968-02-29 DE DE19681639418 patent/DE1639418A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
US3575731A (en) | 1971-04-20 |
GB1224801A (en) | 1971-03-10 |
DE1639418A1 (en) | 1971-02-04 |
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