DE1639418A1 - Method for manufacturing semiconductor devices and semiconductor devices manufactured by the method - Google Patents

Description

Patent application

Process for manufacturing semiconductor devices and semiconductor devices manufactured by the method

The invention relates to a method of manufacturing semiconductor devices and to those made by the method Semiconductor devices. It is particularly concerned with semiconductor devices having at least two epitaxial deposition processes semiconductor areas formed from the vapor phase as well as with processes for the production of such semiconductor devices

At present, the vapor or epitaxial deposition process is used - used for the manufacture of semiconductor sections or semiconductor devices in general offers various advantages »such as easy control of the storatelle concentration of the resulting areas, flawless over-! aisles, shortening for the manufacture of semiconductor areas

009886/0653

required time and precise determination of the strength of the areas. In practice, however, the procedures used have only one semiconductor area by means of the deposition process created. Other 'semiconductor areas are in part of the Deposition process has been produced from the vapor phase by means of the diffusion process. Where the base area is replaced by the Vapor deposition process has been made extremely thin, in order to obtain a greater degree of atrial augmentation, “can a connecting wire cannot be attached to this base region. The diffusion process is therefore opposite to the deposition process has been preferred for forming the base layer or the base region.

It is therefore an object of the invention to provide a semiconductor device with at least two semiconductor areas formed by the vapor deposition process and the electrical Separate or isolate the elements of the "device" so that they have excellent "high current" properties. degree of amplification and very good frequency characteristics on-i

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weis-fcw The procedure itself should consist of simple. Work svor- [ went togetheriii which expire in a relatively short time ■■ - · ■! -. "* .- - - <- = .-.?." '■ ..- "■

It has been shown 4i ° k that the aforementioned Hachteile

of the known methods and that semiconductor devices

directions of, 'high current amplification, excellent |

High frequency and breakdown voltage properties established I

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ÖO9Ö86 / 0S53

© AD OWGLAL

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can be. This is achieved by creating a surface of a semi-conductor underlay with at least one profiled part, ζ. h * a projection or a recess, with a front lateral displacement from the immediate Ilächenbereichen and sides extending ichehbereichen Fl of animal Yorderseitenversetzung to the surrounding, and aurch successively Ixiederschlagen of at least two layers of different Lei tfähigke its types by the vapor-Abseheideverfahren on the flnciie of the outer layer * to cover at least the front and the sides of the protrusion. Then either the inner layer or the outermost layer of the resulting element is removed to a suitable depth so that immediately next to the sides of the junction or the depression a protrusion of at least one layer is exposed on the next layer.

Us: the üefestigunH "empty ßieKtrccte-to dea fcloigelegten ^ uerscaiiitt a niedergescnlagenen splints, for example, the layer containing the Basisbereicli in check easier, it is a iutcrkmai the 3rfindung _r the wirksajEe width at the bloSgeiegten cross section of a selci; s Sciiicht Enlarge, while the desired low thickness remains at the offset front of the crack or the depression. The increase in the effective width at the exposed cross-section can be achieved by kinking the sides, the offset or the depression, so that the plane from which the material is intended

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16394T8

Exposing the cross-section is removed, is aligned obliquely through the corresponding layer. The position of the projection or the depression of the lower layer can also be selected so that its front and sides correspond to the crystal surfaces of relatively small and large growth rates. The effective width of the exposed cross-section einer'Schicht can also Begieren a portion of an adjacent layer or of the-adjacent region of the lower layer are increased, so as to tl ^e i ^c ^ ^ien

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To create conductivity type, or by applyingMMner layer the same conductivity to the adjacent layer or * Lower layer only on the · sides of the protrusion or recess fungus either by the diffusion or the vapor deposition process.

Since all of the layers are deposited on the underlayer by the vapor deposition process, the underlayer can be kept in an oven at all times with the various operations being performed which concern only changes in the types and controlled concentrations of the impurities introduced. In this way , the semiconductor device can be manufactured quickly, and dust or other contaminants cannot be deposited on the underlayer.

It has been found that the method according to the invention is particularly useful in the manufacture of integrated circuits Benefit is because the electrical separation or 'the isolation of the

009886/0653 ". ⁵ "

BATH

Elements of the circle thus obtained "the property

compared with the Eigensoliaf th of the i nt egrie r-fcen "circle- ώΐ-t. Diffusion or dielectric isolation ^{1 of} the i ^ Muienirey the

length "were used, improved *

The aforementioned and other features and benefits
Invention go from the following detailed BeisönreÜJümg
of examples in connection with the drawings. . ^;

Figures 1'ä to TE show schematic Querscihnittsw look at the manufacturing stages of a halving device illustrate according to the known method.

Figures 2A to 2F show schematics
views on manufacturing stages of an i
according to the invention

Figures 5a to 3B show a similar stage of manufacture another embodiment of the invention,

Figures 4A to 4D show a cross section sansicnii en üfeer Production stages of an embodiment of the invention, in which the area for the attachment of an electrode is enlargedν

Figures 5A and 5B show scheioiatisch the various Crystal growth speeds with different crystal surfaces,

Figures 6A to 6E and 7A ^; to 7D each show 'schematic Querachnittsanaichten ^ the procedural stages g

ϊ; AüsfiKnrürigsfοτώ & η of the invention varanschäulichehy ιή AeÄen enlarged "iiereiehe for attaching electrical electrodes αώτ-όη-! Suitable alignment of the crystal surfaces are available.

The Figüriin SA to Bf, 9A to 9fcv TOA to TOE, TIA feis_ / 1 fßy 12A to T2-E and 13A to Τ5Ϊ ¹ of the invention show the versGüiedeiieii Verfäiirens ^ äliüfen other Ausfiihrmngsatufen according ν

In aligemefnen two methods are the so-el ELCT risen en I: ran from individual elements forming an integrated circuit applied. A process is the diffusion isolation process ^; uses the barrier characteristics of semiconductor junction zones (plit junction) formed by diffusion ^: while the other relates to a dielectric insulation method. This method uses insulating materials, e.g. SiÖp, SiC and similar materials. The diffusion isolation method facilitates the manufacture of the integrated circuit and is therefore widely used at present. The consequence is ^, however, that the integrated circuit is poor in its breakdown voltage and high frequency characteristics. Although the integrated dielectric insulation process? Semiconductor circuits are eliminated in their Durchbrucnsspannung and their Hochfre ^ qiuenz-Ohärakteris ^ tikeh niciit so vef, this brings ^ st, -Verfahreh in the manufacture of circuits tangles and t ^#: c - & - "- '""· Schwierigikeiteli inside.

In Fig. 1 it can be seen that when applying the dielectric I sol ie approximately procedure for the preparation of a f ränsistora

one or me.hr ere Vorsprünf e% 2 _f is the great, the fertiggestejll- "th transistor and the area and the shape of, it befind-. ! ions . rT .— ^ bGTgaxLCS , are formed on a semiconductor sublayer 11, sS on a K-Tj "ρ monocrystalline silicon layer. ,, by etching or the like, as shown in Fig. 1A. On vile An insulating layer 13 is deposited on the upper surface of the layer M with aen projections 12, for example by the vapor deposition or epitaxial deposition method, as shown in FIG. 1B. In addition, a polycrystalline silicon layer 14 is deposited on the outer insulating layer 13 formed, for example by the above-mentioned misregistration, as in Fi ^. TiQ shown, oodann the underside of the Jiiizi "u: r, scLicht 11 sanded" and ent lang'der line DD in ri-. 1C '.ve ^ f-eatzt, uai nui * the projections 12 of the lower layer 11 .stwienzuiassen. Each protrusion thus corresponds to the insulating surface of the wall, to the extent to which the scaled surface is in accordance with Fi; -. '1L. Hierau: 'a r-type aasisfcereici: 15 and an N ⁺ -type Eisitterbereioh 16 in the remaining parts of the monokristiiiliiiei: "ü i'Ii zi ύπ -sub-layer 11 with the help of the" selective diffusion \ ^τ ΰη aer ^ resöüliffeneii surface 'formed as in Fi £. 1E is shown. In this way, a diode and a resistor can be made and connected to one another by a lethal vapor deposited on them. In this way, integrated circuits of the dielectric insulation type are created.

009886/0653

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However, this known method does not allow free and precise control of the impurity concentrations and growth in the base and emitter areas, as all semiconductor junctions be formed by the diffusion technique. Furthermore, steady manufacturing processes are impossible because any diffusion process is common takes up to two hours and in each diffusion process Photoresistive and photoetching processes occur.

The present invention avoids the aforementioned pocket parts of the previously used procedures. It becomes = now in context with the example shown in FIG. 2. ·

As FIG. 2A shows, the first step consists in projecting parts 22, which may determine the area and shape of the finished semiconductor junctions (PN junctions), on a semiconductor sub-layer, for example an N ⁺ -type monocrystalline silicon layer to create selective etching of the same. Then, a P-type base layer 23 is deposited on the upper surface of the layer 21 by the vapor deposition method, as shown in Fig. 2B. The N ⁺ -type silicon layer 21 is used as an emitter region in this case. Following the formation of the P-type base layer 23 is determined by the vapor deposition process on said layer an N-type Kollektorschicnt 24 formed according to Fig. 2C, on the layer is deposited in the same way 25 through the already mentioned technique, a N ⁺ -Iyp , Fig. 2D * Above are a layer 26 of insulating

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BATH ORIGINAL

IS3341I

Material, ζ * B. The element resulting from SiOg * - "fine SiG layer 27 and a crystalline silicon layer 28, as shown in I ¹ Ig * 2E" * Pas "is etched and ground on its underside, as shown in FIG. 2E, around the underside to remove the part lying on the line FF or a little more, whereby a semiconductor device according to FIG. 2F is produced. If desired, the etching and grinding can be carried out to such an extent that the polycrystalline silicon layer 28 is exposed.

The above-described method provides the base and collector layers 23 and 24 and therefore easily permits a more precise one Controlling their thickness and their defect concentration gradient " Bs is also possible »an impurity concentration level * were used to maintain the base layer 23, which creates an acceleration field in it * This results in considerable improvements the degree of amplification h _, _, and the characteristics of a Transistor ensured. In addition, there can be all layers 23 to 28 are applied by the vapor deposition process, the application continuously in an oven or in a continuous oven * This means a remarkable simplification of the Manufacturing processes and a considerable saving of time. For example, that is required for a single diffusion process Time about an hour during a vapor deposition processB only takes a few minutes. Also needs in the vapor deposition process the element not removed from the oven to become to cover it, like this for any diffusion process

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163941t

necessary is. Since the element remains in the furnace, contamination of the element by gas and dust is prevented The base and collector layers are formed by a single steam «

The separation process is formed. " a precise control of the concentration of the point of failure to ensure. Therefore, the products according to the method according to the invention have in comparison with those the diffusion process a greater uniformity and better Characteristics

P. Although the invention in the context of the underlayer 21 with the transition areas of the semiconductor located thereon determining projecting parts 22 has been explained, the invention is equally applicable to a sublayer with recessed parts formed in it, as shown in FIGS. JA bis D shows applicable.

In this case, a semiconductor 3A, layer 51, for example.-A P-type monocrystalline silicon sub-layer, subjected to a selective etching to create in their recessed portions 32, soft) will ultimately determine to be obtained semiconductor junction portions, as shown in Fig. is. Then, by the vapor deposition method, a U ^ -type layer 33, an N-type collector layer 34 and a JP-type base layer 35 are deposited on the inner surface of each recessed part 32, one by one, as in Fig. 3B is shown · Furthermore , by the aforementioned method, an N ^ -type lidded layer 36 is likewise formed on the

Base layer 35 is formed, as FIG. 3G illustrates. After that, the resulting element is etched and ground to selectively its part lying above the line D-D, or something more, according to Pig. 3D remove, creating a semiconductor device, namely, an NPH transistor according to FIG. 3D »arises.

In this embodiment, the base layer 35 is also used formed by a single vapor deposition process. Her. Strength can therefore be controlled as desired. Consequently, because the base layer 35 is only 0.5 microns thick can be produced, the degree of electricity enhancement h ~, "and other properties of the transistor can be increased considerably. Furthermore, aixe layers can be applied by the method mentioned so that the operations are carried out continuously in a single furnace with all the advantages mentioned above in the embodiment of FIG.

In the embodiments in FIGS. 2 and 3, the base and collector layers exposed on the outside like this be thin that electrical connections are difficult to make thereon. In the case of the execution form to be described now this difficulty does not arise.

First, as FIG. 4A shows, a semiconductor sublayer 41, for example an N ⁺ -type monocrystalline silicon sublayer, is etched to form a portion protruding thereon of trapezoidal cross-section, ie with inclined sides, which the

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The area of the semiconductor junctions ultimately obtained is determined. In this case, the N ⁺ -type silicon layer 4I serves as an emitter region. Then, a Ϊ-type base layer 43, an N-type collector layer 44, an N ⁺ -type layer 45 and an insulating layer 46, for example, made of SiOp, by means of the vapor deposition method on the entire surface of the protruding Part 42 of layer 41 is deposited sequentially as shown in Fig. 4B. After that, a polycrystalline silicon. layer 47 on the insulating layer 46 formed according to 'FTg. 4C. The resulting element is then etched and ground on its underside, as can be seen in FIG. 4C, to selectively remove the portion or a little more below the line DD. In this way, an NPN transistor according to FIG. 4D is produced.

Since the protruding part 42 is trapezoidal in cross section is, i.e. has sloping sides, the layers are cut diagonally along the line D-D, as can clearly be seen in FIG. 4D leaves. The width of the exposed front or cross-section of each layer is greater than the thickness of the layer itself. Polarity is where the one between adjacent layers lies Base layer 43 is as thin as about 1 micron, for example, the width of the exposed to provide good high frequency properties Front side of the base layer 43 greater than that small thickness, to facilitate the attachment of electrodes to the base layer and thus to simplify the work processes.

009886/0653

0W61NAL

1633418

In the representational embodiment of the part 42 "which determines the portions of the semiconductor junctions of trapezoidal cross-section" formed as a protrusion on the Halbleitersohicht 41Ba is lit; jedoeh a _r that, when a recessed portion of the trapezoidal cross section is formed in the Halbleiterschioht and the semiconductor layers successively are deposited in the recessed part, the attachment of electrodes to a particular semiconductor layer lying between adjacent regions or layers is also similarly facilitated.

In general, the directionality of the crystal growth rate of the diamond type crystal is large according to its crystal structure. For example, if a piece of round monocrystalline silicon rod, the axial direction of which is <111) (general display / Ti ij » ß ^ l / t /" Ti l7 «« ·), a vapor deposition process using a gas of SiHGl is exposed, the cross section of the resulting element will usually be as shown in Fig. 5A. That is, the crystal growth rate in the direction of ζ 110 "> (general display / Tio7» ^ TVo7, £ ~ WQ7 ..,) is greater than those in the Rieh. · '

-...- ■■ \ ^: tion of 211 (general display ^ 511; 71 ^ 21l7 * ^ 21 * 17 · · ·) · Because of the high growth rate, such anisotropy of the crystal is first of the temperature used for crystal growth and secondly, it depends on the type and density of the gas used.

Consequently, in the manufacture of a semiconductor device, an integrated circuit or the like with a vapor deposition method according to the invention, it is possible to achieve rates of crystal growth which narrow the base area, but its exposed area for fixing electrodes by a suitable 7 "'ahl the ivristallflache zoom in to the' transition in the etching of the lower layer and the monokrisfcallinen the semiconductor transition zone determ-_ W- Menden projection or recess to be formed. It has been found that the purpose of the invention is achieved if, for example, the aforementioned protruding part is formed in such a way that its upper surface or surface offset from the surrounding surface areas from the crystal surface föV \ J of low crystal growth rate and its sides from the Crystal faces ^ Ϊ "1Ο7 and /" HO / of high growth rate 3ein, as shown in Fig. 5B.

The aforementioned property is present in the exemplary embodiment in FIG. 6. There is shown a semiconductor lower layer 61, for example made of N ⁺ -type monocrystalline silicon, and a projecting part 62 formed by etching to define the surface area, FIG Partly 6% of the area V / Tit7 of low growth rate and its sides, namely the left and right sides, as in the drawing too

is seen, formed by the areas ^ Tio7 and / 11O7 of great growth rate. Then, a P-type base layer 63 is formed on its upper surface of the underlayer 61, as in Yic '. 6b is shown. In this case, the N ^ -type monocrystalline silicon layer 61 is not used as an emitter. Furthermore, a !! - ^{-type collector layer 64 »a K +} -type layer 65 and. an insulating layer 66, for example made of SiOp, is deposited one after the other according to FIG. 6C. A monocrystalline silicon layer 67 is then formed on the insulating layer 6b in the same way as shown in FIG. 6B. Finally, the resulting element is etched and ground on its underside, as can be seen in FIG. 6D, up to the line EE or something higher. Thus, an NPK transistor "shown in FIG. 6E" is obtained.:

Since the area of the protruding part is 6.2, that is the Area / ^ VX7r a smaller crystal growth rate than both sides, namely the areas / TtO / and </ "" 11 C? 7, are the parts of the base layer 63 »the collector layer 64» the N-type layer 65 etc., which is over the top surface of the protruding Part 62 lie thinner than those formed on the sides, with the difference in thickness being determined by the difference between the crystal growth rates is determined. Therefore, even if the thickness of the base layer 63 is in the Direction of O11} is as thin as e.g. 1 micron, the base layer 63 in the direction of O10} should be made thick enough to attach it an electrode on the layer to facilitate.

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BATH ORIGINAL

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Although the semiconductor underside in Pig. 6 a protruding Has part in order to determine the area and the shape of the semiconductor junctions, the feature of the invention shown there can in a similar manner with an underlayer a recess, as will be described later in connection with FIG. 7.

The method shown in FIG. 7 begins with the formation, for example by selective etching, of a recessed part 72 in a semiconductor underlayer 71, for example of the P -type monocrystalline silicon, as shown in FIG. 7A. In this case, the base of the recessed part 72 is the crystal face / T11_7 of a slow crystal growth rate, while both side walls, namely the left and right side walls in the drawing, are formed by the crystal faces / T1O7 and 11O7 of a high crystal growth rate After forming the recessed part 72, an N ⁺ -type layer 73 and an N-type collector layer 74 are successively deposited on the inner surface of the recessed part 72 by the vapor deposition method, as shown in FIG Further, a P-type base layer 75 and an N ⁺ -type emitter layer 76 are similarly formed on the collector layer 74, as shown in Fig. 7C, and then the resulting element is etched on its underside and ground until to line DD or a little beyond, creating an NPN transistor as shown in Fig. 7D.

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009886/065 3

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If .

Here again * the base of the recessed part 72, that is the crystal surface ^ Tt | J%, a smaller structure of growth than both side walls * of course the crystal surfaces ^ ΐϊ © 7 üß & C ~ * $ t Jia- V Ii ⁺ -T3fi> * SchiCfct 731 parts def KöllektorscMöiit 74 * the BaSisäcbiGtit 75 üäfvr _"r dieüfeer the E-ruiidfläcsJie of Afeitieften part 72 αϋίίϋιβΐ gemaöiit Wei ¹ * of the parts as diesei · SehieMea on deji Seiteüwändeit according dei? Difference in the calf pace speed of the baker can, like züV or freeeirieben, the electrodes can be easily attached to the baker «· ~ '

In a Versueiien a gas Sihol, Irei _f denen.zur in formation of a temperature of 1100% benittzt '

was, the strength of the sight in the biciitüng was τοη ^ l 11 ^ two microns and that of the ScMoIit in the sighting of ζ \ 10 ^ five microns «

In Figures 6 and 7, the sides of the projecting head 62 and the recessed portion 72 of the ball ladder with it layer perpendicular to their front side, which are "offset with respect to the surrounding surfaces of the overlapping" * However, in the embodiments of FIGS 7 ^ i ^ sides of the projecting and recessed parts of the ink rs should be inclined, as already described with reference to Fig. 4. As a result, the real width of the exposed cross-section, the spring layer for attaching an elec- trode, is even greater. "

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009 IM / ÖM p

1639411

lei the execution example according to Fig. 8 is a half

8t, z * S «from N -Tyρ mono-crystalline silicon, with a; then an iH-type base layer 83 * a K-type detector layer 84 * an N ^ -type layer 85, an insulating layer 86 made of silicon or the like and a polycrystalline layer are formed, as shown in FIGS Silicon layer SJ nööeinandeir deposited on the upper surface of the lower layer 81, as shown in Fig. 8B *. The resulting element is then etched and ground from its underside to the line Ö-ß or a little beyond, in order to create a HPN-Tfahsistor according to Fig. 8C to create "After this, a resistant layer 88ι z # B. formed from SiO ₂ ι on the bottom surface of the transistor, and the portion of the layer 88 overlying the emitter region 81 and the base region 83 is selectively removed by etching to create an aperture or a cavity region. A metal such as aluminum is then deposited in the aperture or cavity area. As a result, an additional base region 89 is created from an alloy layer in a selected part of the emitter region 8t, while at the same time a base electrode SOb according to FIG. 8B is formed with the vapor-deposited metal , deposited on the collector layer 84 and the S ⁺ -type layer 85 du ^ eh damp so that an ohmic contact and thus a collector electrode 80c is formed, as shown in Fig. 8E.

1639A18

In the arrangement described above, the easie area consists of the base layer 83 and the additional ^^ base area 89 of the same type of conductivity, so that the Area of the base area is enlarged. The base electrode 8Cb arises at the same time on the base area.

The considerations in the development of the invention, tests, the aluminum forms when it is deposited on an N-type silicon at 510 ⁰ C for three .Minuten and the 'temperature then increases to 580 ° and 59 ° ⁰ G e% ne Alloy layer with the N-type silicon, as at 89 · The deposited aluminum also forms an ohmic with the N-type silicon when it is deposited at 50 ⁰ C for fifteen seconds and the resulting element is then left for three minutes Contact, as with. 80c. Of course, metals other than aluminum can also be used - provided they are able to form an alloy layer or an ohmic contact.

Although the foregoing relates primarily to a semiconductor underlayer 81 having a protruding portion 82 defining the transition region, it is clear that if, in a recessed portion in an underlayer, semiconductor regions are successively formed in the concave portion, as in FIGS. 2 and 7 , an equal additional semiconductor region an alloy layer is produced _r to those described above with reference to Fig. 8 the same. '-

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In Pig. 9, another example of the invention is shown in which an N -type monocrystalline silicon underlayer 91 with a protruding portion 92 is first formed. An insulating layer 93 made of SiQ ₂ »SiC or the like is applied to its front side, as shown in FIG. 9A. The insulating layer can easily be made by applying a coating of SiOp over the entire surface of a flat monocrystalline silicon sub-layer and then selectively etching the coating and the sub-layer Insulating layer 93 serves as a cover panel. This creates an additional P-type base layer 94 as shown in FIG. 9B. In this case, the silicon layer 91 serves as an emitter area. Subsequent to the formation of the additional base layer 9'4, the insulating layer 93 is removed, whereupon a P-type base layer 95, a ϊϊ-type collector ^{layer 96, an N +} -type layer 97 and an insulating layer 98 made of SiOp in succession be deposited on the underlayer 91 as shown in Fig. 9C by the vapor deposition method. Further, a polycrystalline silicon layer 99 is continuously formed on the insulating layer 98 as shown in FIG. 9D. The resulting element is then etched and ground from its underside to line EE, to form a KPN transistor as shown in FIG. 9E. Since the additional base region 94 is previously produced on the side walls of the protruding part 92 by means of the diffusion process

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is, the final effective base area consists of the additional base layer $$ and the base layer 95. It follows that the base area is wide at the part to which the base electrode is applied, while the central part is wide of the base region, which extends through the surface of the protruding part 92 and is closely related to the characteristics of the semiconductor device, is extremely thin because it is a semiconductor region formed only by a single vapor deposition process. Therefore, this central part of the base region can be used is extremely thin, the, BaaiselefctrOde easily and without difficulty to the base-bereieh attached who * the "Furthermore, the semiconductor layers may be prepared by the deposition * - be moved after removal of the insulating layer 95 in a single furnace successively formed so that the already mentioned Advantages of the invention can be achieved.

When the additional base layer 94 is formed by diffusing a P-type impurity into the N * -0 * yp emitter region 91. dxe Biffusipn 'difficult to produce if the emitter area is very enriched. To overcome these Schwierigkeiii, one silicon sublayer 91 Itt heated to a vacuum and lowers the Störatellenfconzentration the surface aο of the part 92, which ultimately ^ as - type emitter is used .. The!; is of course not necessary if the lower layer is not eye ** enriched. '

009086/0653

ORIGINAL

163941S

Fig. 10 illustrates another example of the invention showing a semiconductor sub-slide formed with a recessed file 102 instead of a protruding portion as in Fig. 9, this recessed file is first formed in a P-type monocrystalline silicon layer 101 thereafter An If ⁺ -Ty p-layer 105 and an N-type collector layer 104 are successively formed on the surfaces defining the recessed part 102, as shown in FIG. 4, IQA. dejected. An insulating layer 105, ζ · Β.-made of SiO ₂ f, is then formed on the collector layer 104 at the bottom of the recess, as shown in FIG. 10B. Thereafter, an additional P-type base layer 106 is formed in the collector layer 104 by a diffusion process in which the insulating layer 105 serves as a cover panel, as shown in FIG. IOC. After removing the insulating layer 105, a P-type base layer 107 and a W ⁺ -type emitter layer 108 are deposited one after the other by the vapor deposition method, as shown in FIG. 10 ©. Thereupon the emerging element becomes of his, upper one

^ Area etched down to line E-E or slightly beyond ^; and sanded. The result is an NPII transistor shown in FIG. 10E. ^; -.-. ■: ■ --- ■

Fig. 11 shows yet another embodiment of the invention. It is the same as that of Fig. 9 except the application of the vapor separation process. There are therefore in Fig. the parts which are the same as in Fig. 9, with the same

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EADORfGiNAL

Zugsziffer.bezeicLnet ,. In one made according to this example The Ba8.isbe.reIcJa transistor is also essential in the part thickened, on which the base electrode lies, while its IUt divides part, which determines the properties of the transistor, can be very thin "as FIG. 11E" shows, because he semiconductor area deposited by a single deposition process is. Therefore, the thin base portion does not cause any difficulty in attaching the base electrode. Furthermore, the semiconductor layers can already be used several times mentioned. Continuous deposition process in a single furnace are formed after -.- 'the insulating layer 93 has been removed. This simplifies the manufacturing process and shortens the time required for this.

Figure AZ illustrates another example of the invention; it is the same as the example of Fig. 10 except for the use of the vapor deposition process to form an additional base layer 126. Here again the parts that are the same as those of Fig. 1.0 are denoted by the same reference numerals. A description in this regard is not given. This example has the same advantages as the example according to FIG. 10.

... In the finally in Fig. -13 example shown is a first insulating layer 132, for example, of SiO _2, the entire upper surface of a semiconductor layer -1.31, for example from

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ORIGINAL

P-type ffionokristallinem silicon, dejected, are removed by etching after which selected areas of the insulating layer to provide apertures 153, as shown in Mg. Is illustrated 13A * Subsequently, an N ⁺ -type impurity is diffused through each aperture in the silicon sublayer 131 . It forms therein an emitter region 134 according to FIG. 13B. The underlayer is then subjected to an etching process in order to remove the insulating layer 132 and parts of the underlayer which surround the emitter area. What remains are the emitter regions 134 and the base regions 135 surrounding them, which protrude beyond the remainder of the lower layer 131, as is shown in FIG. 13.0. Then a P-type base layer 136, an N-type collector layer 137 »an Ii ⁺ - type layer 138 and an insulating layer 139f, for example * made of SiQ ₂ *, are deposited one after the other on the silicon layer 131 by the method already mentioned, FIG. 13D. Further, a polycrystalline layer 130 is deposited on the insulating layer 139 in the same manner, as shown in Fig. 13E. The resulting element is etched and ground from its underside to the line 3MF in Fig. 13E, thus giving a semiconductor device of the type shown in Fig. 13F where the exposed base 135 "and base layer 136 provide a relatively wide area for mounting the base electrode *

The invention has been previously discussed in connection with the production of HPH Traneistoren "She eats | edoöh APEA $ rei other ~ H lbleiteTroTTiöhtm $ ® & [wMWBnähm ^ t Wim". ". & .B · at _.PNP- -.

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BATH

1039418

Transistors, NtP transistors, integrated circuits, switching devices etc. It is also clear that the process of formation of semiconductor areas, their conductivity types, the process for the formation of insulating layers, the shapes and types of the semiconductor sub-layers are not limited to the exemplary embodiments described, but can be modified as desired. .

In the method according to the invention one is preferred Lower layer that is covered with a storable substance such as antimony, arsenic or dergl «, instead of being enriched with phosphorus and a gaseous one SiH, instead of SiCl, for the steam absorption process. the temperature used is preferably slightly low hold so as not to cause the growth to crystallize damage.

Of course, numerous changes and modifications can be made in addition to the exemplary embodiments described here be made without affecting the scope and meaning of the Invention deviate.

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0098 8 6/0653 ^ÖÄD

Claims (18)

PATBN TA HSPR ü O St. A method of manufacturing a semiconductor device comprising the steps of forming a surface of a semiconductor underlayer comprising at least one profiled part ^ which part a dislocation surface against the surrounding areas of said Has surface and sides that extend from the dislocation surface to the surrounding areas, characterized thereby- * indicates that on the semiconductor underlayer with the help of the vapor deposition process successively at least two layers of different Conductivity types are precipitated to at least the dislocation surface and its sides of the profiled - To cover part and that of the emerging element selectively Sufficient material is removed in order to have a cross-section at least from the am in addition to the said sides of the profiled part to expose the next lying layer. 2. The method according to claim 1, characterized in that the "called sides of the profiled part are inclined so that the ι The width of the exposed cross-section of a layer is significantly ■■! ι is greater than its strength to darsjh attaching an electrode to facilitate. :: "■ j 3 «The method according to claim 1, characterized in that the ■ the profiled part [is offset from the mentioned lower layer, so - 27 000886/0653 BATH -27 '■ -' ■■ .- "." "■■ Λ -;" -. ■ that said surface of the profiled part corresponds to a crystal surface of relatively low crystal growth rate , and at least one of the said sides of the profiled part corresponds to a crystal surface of relatively high crystal growth rate, whereby the layer closest to said profiled part is on one said side of the profiled part part is thicker to facilitate than on said surface of the latter "to ύ ie fixing an electrode on the freigelegtem cross-sectional" 4. The method according to claim 1 _f thereby .geimgeichnet _? that pin surface area of the semiconductor device is alloyed next to one of the layers mentioned with an exposed cross-section. " so that he has the same thing as MtWuhtgkeitmtjp Mat. “I left a layer, which makes it easier to use this layer 5. The method according to claim ".1, äaiureli g @ fe" iasiaeicshpet _t . That before the knocking down of the first of the named "Sehieiiten" to cover the named Lleh © uM ^; Sides aee genaaateö profiled part at least only on the axed sides -d @ s profiled part a layer of fiem.gX@iöhnahma feitbarkeitstirp; like slat of the: mentioned first layer down ^ gea. tJte #. ₈ so & ai @ise relatively large width. Of conductivity type © - the first sweetness at ■ whose exposed transverse area ztpp leichtea Baftsstigiaiig © iaer electrode is given on it. 6 »Method according to claim 5» characterized in that, did the layer that is only deposited on the sides of the profiled ifils mentioned on the d, ön is diffused on. 7. The method according to claim 5, characterized in that the only dejected on the named sides of the profiled leil Layer is also applied using the vapor deposition process * 8 «Method according to claim 1 _f, characterized» that before the said layers are deposited, impurities are diffused into a region of the said surface which is smaller than the region of the said surface of the profiled part and lies in it, in order to have a conductivity type therein create, which is opposite to that of said sublayer, and that the era-fce 4er deposited on the sublayer said layers of the same conductivity as that of said sublayer, so that the area of the exposed cross section of said first layer is effectively increased by the adjacent exposed area of said sub-layer of the same type of conductivity, in order to facilitate the attachment of an electrode to said first layer » 9. The method according to claim Ö # characterized in that the Disturbance in called an area of the underlayer prior to formation -29 - 009886/0 SS diffuses the said surface with said profiled part will. . 10. The method according to claim Λ »characterized in that the profiled part is a projection (eg 22 _f Fig * 2A), and the said material is removed from the surface of the underlayer (eg» 21, Pig · 2A), opposite; to the aforementioned surface formed with a projection in order to leave only the profiled part of the lower layer standing, 11. The method according to claim 1, characterized in that said profiled part is a recess (ζ · Β. 32 ", Tig.3iT", " that of the most recently struck down of the layers mentioned is filled in and that said material from the surface of the element formed by said layers is removed in order to the cross-section of the layers mentioned within the said layers To expose the recess (e.g. Fig. 3D) U S 12. Semiconductor device with a base and at least a recess located in it, characterized in that at least two different vapor deposited layers Conductivity over the sides and bottom of the well (e.g. 32, Pig, 3A), and a semiconductor material that can accommodate the fills the remaining part of the recess, and that at least an-i
filling material and the next / lying layer on the top - 30 009886/0653 exposed cross-sections (e.g. Fig, 3D). 13. Semiconductor device according to claim 12, characterized in that that the sides of said recess are inclined, so that said exposed cross-section of a layer transversely is obliquely aligned by it * 14 »Semiconductor device according to claim 12, characterized in that that the layers are deposited by vapor in order to achieve greater crystal growth rates on the sides of the said Recess than at the bottom of the recess to "reach". 15. The semiconductor device according to claim 12, characterized in that that said filler material has alloyed layers, the exposed cross section of the closest to the named Adjacent layer and of the same conductivity as the ) are the latter.] 'I ; '■■■ J' ■■ '■■ · ^./: ■■' ■ '■■ ■! ^; ■:. (- .:. ■■■■; ■ ■. ■■; · ■ ■■:. ■■■■■.! 16. Semiconductor device according to claim 12 _1, characterized in that I draws that the filling material side areas with diffuü- in it; dated interfering substances, so that it has the same conductivity speed is like the mentioned next layer. 009886/0653 ßAD OFf / GINAL 17. Semiconductors * 0r3 ^ ehttihg according to Kn & pTück t ^ diidurcii characterized that a duron paaipf grown layer between the sides of the mentioned filling material and the sides of the adjacent of the mentioned rails "which lie over the sides and the bottom of the recess *!" is laid and is of the same quality as the above-mentioned a closest schioiit "* 18. Ha ^ bieitervorciöh / toag ^ ! features "that said ftillmaterial same from the ^" ince "fähiglceit is as said nächstliegeiide layer, and materials of the center region of said Püilmateriais diffused in sturgeon, has so that he gets the opposite läeitfähiglceit · -. - ' -. {'. - ■ ': -λ.-.'.-> -. _.;: ': ■}.'. ^;