DE2554536C2 - Verfahren zum Bestimmen der Breite und/oder des Schichtwiderstandes von flächenhaften Leiterzügen integrierter Schaltungen - Google Patents

Verfahren zum Bestimmen der Breite und/oder des Schichtwiderstandes von flächenhaften Leiterzügen integrierter Schaltungen

Info

Publication number
DE2554536C2
DE2554536C2 DE2554536A DE2554536A DE2554536C2 DE 2554536 C2 DE2554536 C2 DE 2554536C2 DE 2554536 A DE2554536 A DE 2554536A DE 2554536 A DE2554536 A DE 2554536A DE 2554536 C2 DE2554536 C2 DE 2554536C2
Authority
DE
Germany
Prior art keywords
conductor tracks
width
conductor
sheet resistance
integrated circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2554536A
Other languages
German (de)
English (en)
Other versions
DE2554536A1 (de
Inventor
Donald Ralph Westford Vt. Thomas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2554536A1 publication Critical patent/DE2554536A1/de
Application granted granted Critical
Publication of DE2554536C2 publication Critical patent/DE2554536C2/de
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/08Measuring resistance by measuring both voltage and current
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Measurement Of Resistance Or Impedance (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
DE2554536A 1975-01-02 1975-12-04 Verfahren zum Bestimmen der Breite und/oder des Schichtwiderstandes von flächenhaften Leiterzügen integrierter Schaltungen Expired DE2554536C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/538,288 US3974443A (en) 1975-01-02 1975-01-02 Conductive line width and resistivity measuring system

Publications (2)

Publication Number Publication Date
DE2554536A1 DE2554536A1 (de) 1976-07-08
DE2554536C2 true DE2554536C2 (de) 1986-04-17

Family

ID=24146264

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2554536A Expired DE2554536C2 (de) 1975-01-02 1975-12-04 Verfahren zum Bestimmen der Breite und/oder des Schichtwiderstandes von flächenhaften Leiterzügen integrierter Schaltungen

Country Status (5)

Country Link
US (1) US3974443A (US06534493-20030318-C00166.png)
JP (1) JPS5845816B2 (US06534493-20030318-C00166.png)
DE (1) DE2554536C2 (US06534493-20030318-C00166.png)
FR (1) FR2296852A1 (US06534493-20030318-C00166.png)
GB (1) GB1479869A (US06534493-20030318-C00166.png)

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US4672314A (en) * 1985-04-12 1987-06-09 Rca Corporation Comprehensive semiconductor test structure
FR2618021B1 (fr) * 1987-07-07 1990-01-05 Thomson Semiconducteurs Structure et procede de test pour circuit integre permettant la determination des effets de surface de couches
US4797604A (en) * 1987-12-09 1989-01-10 Etcon Corporation Wire length meter suppling current to a wire from which a signal representative of length is derived
JPH01184935A (ja) * 1988-01-20 1989-07-24 Toshiba Corp 半導体装置
US4922182A (en) * 1988-08-03 1990-05-01 Monroe Electronics, Inc. Auto reactance compensated non-contacting resistivity measuring device
US4918377A (en) * 1988-12-05 1990-04-17 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Integrated circuit reliability testing
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US4978923A (en) * 1989-04-26 1990-12-18 Ron Maltiel Electrical measurements of the profile of semiconductor devices during their manufacturing process
US5044750A (en) * 1990-08-13 1991-09-03 National Semiconductor Corporation Method for checking lithography critical dimensions
US5082792A (en) * 1990-08-15 1992-01-21 Lsi Logic Corporation Forming a physical structure on an integrated circuit device and determining its size by measurement of resistance
US5602492A (en) * 1992-03-13 1997-02-11 The United States Of America As Represented By The Secretary Of Commerce Electrical test structure and method for measuring the relative locations of conducting features on an insulating substrate
US5617340A (en) * 1994-04-28 1997-04-01 The United States Of America As Represented By The Secretary Of Commerce Method and reference standards for measuring overlay in multilayer structures, and for calibrating imaging equipment as used in semiconductor manufacturing
US5247262A (en) * 1992-03-13 1993-09-21 The United States Of America As Represented By The Secretary Of Commerce Linewidth micro-bridge test structure
US5857258A (en) * 1992-03-13 1999-01-12 The United States Of America As Represented By The Secretary Of Commerce Electrical test structure and method for measuring the relative locations of conductive features on an insulating substrate
US5383136A (en) * 1992-03-13 1995-01-17 The United States Of America As Represented By The Secretary Of Commerce Electrical test structure and method for measuring the relative locations of conducting features on an insulating substrate
EP0578899B1 (en) * 1992-07-15 1996-12-27 STMicroelectronics S.r.l. Process for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said process
FR2706042B1 (fr) * 1993-06-03 1995-08-11 Matra Cap Systems Sa Procédé de contrôle des pistes d'un circuit d'interconnexion et circuit permettant de mette en Óoeuvre un tel procédé.
WO1995007469A1 (en) * 1993-09-08 1995-03-16 THE UNITED STATES OF AMERICA, represented by THE SECRETARY, DEPARTMENT OF COMMERCE Non-contact linewidth measurement of semiconductor conductors
US5485080A (en) * 1993-09-08 1996-01-16 The United States Of America As Represented By The Secretary Of Commerce Non-contact measurement of linewidths of conductors in semiconductor device structures
EP0685881A1 (en) * 1994-05-31 1995-12-06 AT&T Corp. Linewidth control apparatus and method
US5777486A (en) * 1994-10-03 1998-07-07 United Microelectronics Corporation Electromigration test pattern simulating semiconductor components
US5552718A (en) * 1995-01-04 1996-09-03 International Business Machines Corp. Electrical test structure and method for space and line measurement
JPH0972870A (ja) * 1995-07-06 1997-03-18 Toyota Central Res & Dev Lab Inc 劣化検出方法及び劣化検出装置
KR100223924B1 (ko) * 1996-07-19 1999-10-15 구본준 전극의 라인폭을 측정하기 위한 테스트패턴
US6239604B1 (en) * 1996-10-04 2001-05-29 U.S. Philips Corporation Method for inspecting an integrated circuit by measuring a voltage drop in a supply line of sub-circuit thereof
US5963784A (en) * 1997-05-09 1999-10-05 Vlsi Technology, Inc. Methods of determining parameters of a semiconductor device and the width of an insulative spacer of a semiconductor device
KR100272659B1 (ko) * 1997-06-28 2000-12-01 김영환 반도체 소자의 금속배선 선폭 측정방법
US6057171A (en) * 1997-09-25 2000-05-02 Frequency Technology, Inc. Methods for determining on-chip interconnect process parameters
DE60114401T2 (de) * 2000-01-21 2006-08-03 Infineon Technologies Ag Verfahren und system zur kalibrierung einer elektrischen messung der linienbreite und in dem verfahren genutzter wafer
KR100336792B1 (ko) * 2000-05-25 2002-05-16 박종섭 실리사이드막 제조공정의 평가를 위한 시험 패턴의 구조
US7183623B2 (en) * 2001-10-02 2007-02-27 Agere Systems Inc. Trimmed integrated circuits with fuse circuits
US6747445B2 (en) 2001-10-31 2004-06-08 Agere Systems Inc. Stress migration test structure and method therefor
JP3652671B2 (ja) * 2002-05-24 2005-05-25 沖電気工業株式会社 測定用配線パターン及びその測定方法
JP2005091065A (ja) * 2003-09-16 2005-04-07 Oki Electric Ind Co Ltd 半導体装置への動作電圧供給装置及び動作電圧供給方法
US7119571B2 (en) * 2004-11-24 2006-10-10 Applied Materials, Inc. Test structure design for reliability test
KR100828512B1 (ko) * 2005-10-11 2008-05-13 삼성전기주식회사 개방 및 단락의 동시 모니터링이 가능한 반도체 칩 패키지
US7902849B2 (en) * 2006-01-03 2011-03-08 Applied Materials Israel, Ltd. Apparatus and method for test structure inspection
US7750660B2 (en) * 2006-03-30 2010-07-06 Qualcomm Incorporated Integrated circuit with improved test capability via reduced pin count
DE102006025365B4 (de) * 2006-05-31 2010-10-07 Advanced Micro Devices, Inc., Sunnyvale Teststruktur zum Abschätzen von Elektromigrationseffekten, die durch poröse Barrierenmaterialien hervorgerufen werden
US7514940B1 (en) * 2006-12-13 2009-04-07 National Semiconductor Corporation System and method for determining effective channel dimensions of metal oxide semiconductor devices
US8013400B1 (en) 2008-04-21 2011-09-06 National Semiconductor Corporation Method and system for scaling channel length
US9252202B2 (en) * 2011-08-23 2016-02-02 Wafertech, Llc Test structure and method for determining overlay accuracy in semiconductor devices using resistance measurement
US9159646B2 (en) 2012-12-13 2015-10-13 Intel Corporation Apparatus and method to monitor die edge defects

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US2659862A (en) * 1951-11-01 1953-11-17 Branson Instr Apparatus for electrical measurement of thickness using current ratios
US2659861A (en) * 1951-11-01 1953-11-17 Branson Instr Apparatus for electrical thickness measurement
US2854626A (en) * 1954-12-31 1958-09-30 Davidson Martin Plating thickness indicator
US3134077A (en) * 1961-09-18 1964-05-19 Tektronix Inc Electrical probe apparatus for measuring the characteristics of semiconductor material
CH399588A (de) * 1962-07-17 1965-09-30 Siemens Ag Verfahren zum Bestimmen des spezifischen Widerstandes einer dünnen Halbleiterschicht
US3335340A (en) * 1964-02-24 1967-08-08 Ibm Combined transistor and testing structures and fabrication thereof
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GB1320122A (en) * 1971-01-15 1973-06-13 Fulmer Res Inst Ltd Method and equipment for the determination of the degree of abrasiveness of magnetic tape
US3808527A (en) * 1973-06-28 1974-04-30 Ibm Alignment determining system

Also Published As

Publication number Publication date
FR2296852B1 (US06534493-20030318-C00166.png) 1978-05-12
JPS5190573A (US06534493-20030318-C00166.png) 1976-08-09
JPS5845816B2 (ja) 1983-10-12
FR2296852A1 (fr) 1976-07-30
DE2554536A1 (de) 1976-07-08
GB1479869A (en) 1977-07-13
US3974443A (en) 1976-08-10

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Legal Events

Date Code Title Description
OD Request for examination
8128 New person/name/address of the agent

Representative=s name: NEULAND, J., DIPL.-ING., PAT.-ASS., 7030 BOEBLINGE

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee