DE2352138A1 - Verfahren zum herstellen einer halbleiteranordnung - Google Patents

Verfahren zum herstellen einer halbleiteranordnung

Info

Publication number
DE2352138A1
DE2352138A1 DE19732352138 DE2352138A DE2352138A1 DE 2352138 A1 DE2352138 A1 DE 2352138A1 DE 19732352138 DE19732352138 DE 19732352138 DE 2352138 A DE2352138 A DE 2352138A DE 2352138 A1 DE2352138 A1 DE 2352138A1
Authority
DE
Germany
Prior art keywords
organic
layer
insulating layer
inorganic insulating
added
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19732352138
Other languages
German (de)
English (en)
Inventor
Erich Dipl Chem Dr Pammer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Priority to DE19732352138 priority Critical patent/DE2352138A1/de
Priority to GB4287974A priority patent/GB1447843A/en
Priority to FR7434080A priority patent/FR2248614B1/fr
Priority to CA211,481A priority patent/CA1021469A/en
Priority to IT28472/74A priority patent/IT1022912B/it
Priority to JP49119854A priority patent/JPS5080084A/ja
Priority to US05/515,604 priority patent/US3984588A/en
Publication of DE2352138A1 publication Critical patent/DE2352138A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/47—Encapsulations, e.g. protective coatings characterised by their materials comprising organic materials, e.g. plastics or resins
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Electrodes Of Semiconductors (AREA)
DE19732352138 1973-10-17 1973-10-17 Verfahren zum herstellen einer halbleiteranordnung Pending DE2352138A1 (de)

Priority Applications (7)

Application Number Priority Date Filing Date Title
DE19732352138 DE2352138A1 (de) 1973-10-17 1973-10-17 Verfahren zum herstellen einer halbleiteranordnung
GB4287974A GB1447843A (en) 1973-10-17 1974-10-03 Semiconductor devices
FR7434080A FR2248614B1 (enExample) 1973-10-17 1974-10-10
CA211,481A CA1021469A (en) 1973-10-17 1974-10-16 Process for producing a semiconductor arrangement having a metal contact layer between two insulating layers
IT28472/74A IT1022912B (it) 1973-10-17 1974-10-16 Procedimento per fabbricare un dispositivo a semiconduttori
JP49119854A JPS5080084A (enExample) 1973-10-17 1974-10-17
US05/515,604 US3984588A (en) 1973-10-17 1974-10-17 Semiconductor structures and method of producing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19732352138 DE2352138A1 (de) 1973-10-17 1973-10-17 Verfahren zum herstellen einer halbleiteranordnung

Publications (1)

Publication Number Publication Date
DE2352138A1 true DE2352138A1 (de) 1975-04-30

Family

ID=5895702

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732352138 Pending DE2352138A1 (de) 1973-10-17 1973-10-17 Verfahren zum herstellen einer halbleiteranordnung

Country Status (7)

Country Link
US (1) US3984588A (enExample)
JP (1) JPS5080084A (enExample)
CA (1) CA1021469A (enExample)
DE (1) DE2352138A1 (enExample)
FR (1) FR2248614B1 (enExample)
GB (1) GB1447843A (enExample)
IT (1) IT1022912B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3837826A1 (de) * 1988-11-08 1990-05-10 Nokia Unterhaltungselektronik Verfahren zum beschichten einer substratplatte fuer eine fluessigkristallzelle

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5772104A (en) * 1996-08-26 1998-06-30 Peerless Of America Incorporated Methods of brazing and preparing articles for brazing, and coating composition for use in such methods

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3020156A (en) * 1957-05-10 1962-02-06 Mycalex Corp Of America Method of coating metal on dielectric material
US3222173A (en) * 1961-05-15 1965-12-07 Vitramon Inc Method of making an electrical unit
US3443944A (en) * 1963-10-23 1969-05-13 United Aircraft Corp Method of depositing conductive patterns on a substrate
US3518751A (en) * 1967-05-25 1970-07-07 Hughes Aircraft Co Electrical connection and/or mounting arrays for integrated circuit chips
US3775117A (en) * 1971-07-13 1973-11-27 Siemens Ag Process for selective metallization of insulating material bodies
GB1384028A (en) * 1972-08-21 1974-02-12 Hughes Aircraft Co Method of making a semiconductor device
US3936531A (en) * 1973-05-01 1976-02-03 Union Carbide Corporation Masking process with thermal destruction of edges of mask

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3837826A1 (de) * 1988-11-08 1990-05-10 Nokia Unterhaltungselektronik Verfahren zum beschichten einer substratplatte fuer eine fluessigkristallzelle

Also Published As

Publication number Publication date
GB1447843A (en) 1976-09-02
CA1021469A (en) 1977-11-22
JPS5080084A (enExample) 1975-06-28
FR2248614B1 (enExample) 1978-11-24
IT1022912B (it) 1978-04-20
FR2248614A1 (enExample) 1975-05-16
US3984588A (en) 1976-10-05

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