DE2325922C2 - Aus Schieberegistern aufgebaute Speicheranordnung mit dynamischer Umordnung - Google Patents

Aus Schieberegistern aufgebaute Speicheranordnung mit dynamischer Umordnung

Info

Publication number
DE2325922C2
DE2325922C2 DE2325922A DE2325922A DE2325922C2 DE 2325922 C2 DE2325922 C2 DE 2325922C2 DE 2325922 A DE2325922 A DE 2325922A DE 2325922 A DE2325922 A DE 2325922A DE 2325922 C2 DE2325922 C2 DE 2325922C2
Authority
DE
Germany
Prior art keywords
shift register
shift
memory arrangement
data
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2325922A
Other languages
German (de)
English (en)
Other versions
DE2325922A1 (de
Inventor
William Francis Hopewell Junction N.Y. Beausoleil
Irving Tze Poughkeepsie N.Y. Ho
Hwa Nien Yorktown Heights N.Y. Yu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2325922A1 publication Critical patent/DE2325922A1/de
Application granted granted Critical
Publication of DE2325922C2 publication Critical patent/DE2325922C2/de
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/007Digital input from or digital output to memories of the shift register type
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]
    • G11C19/285Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C19/00Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287Organisation of a multiplicity of shift registers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1057Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components comprising charge coupled devices [CCD] or charge injection devices [CID]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Human Computer Interaction (AREA)
  • General Engineering & Computer Science (AREA)
  • Shift Register Type Memory (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Memory System (AREA)
DE2325922A 1972-07-03 1973-05-22 Aus Schieberegistern aufgebaute Speicheranordnung mit dynamischer Umordnung Expired DE2325922C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26834272A 1972-07-03 1972-07-03

Publications (2)

Publication Number Publication Date
DE2325922A1 DE2325922A1 (de) 1974-01-24
DE2325922C2 true DE2325922C2 (de) 1983-03-31

Family

ID=23022543

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2325922A Expired DE2325922C2 (de) 1972-07-03 1973-05-22 Aus Schieberegistern aufgebaute Speicheranordnung mit dynamischer Umordnung

Country Status (7)

Country Link
US (1) US3789247A (US08124317-20120228-C00034.png)
JP (1) JPS532304B2 (US08124317-20120228-C00034.png)
CA (1) CA982238A (US08124317-20120228-C00034.png)
DE (1) DE2325922C2 (US08124317-20120228-C00034.png)
FR (1) FR2191208B1 (US08124317-20120228-C00034.png)
GB (1) GB1386729A (US08124317-20120228-C00034.png)
IT (1) IT988995B (US08124317-20120228-C00034.png)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7311429A (nl) * 1973-08-20 1975-02-24 Philips Nv Opneeminrichting uitgevoerd met informatie- opneemplaatsen in een halfgeleiderlichaam.
DE2427173B2 (de) * 1974-06-05 1976-10-21 Siemens AG, 1000 Berlin und 8000 München Einrichtung zum verschieben von ladungen nach freier wahl in eine vorgegebene richtung oder in die entgegengesetzte richtung und zum speichern von ladungen mit einer ladungsgekoppelten ladungsverschiebeanordnung
US3986059A (en) * 1975-04-18 1976-10-12 Bell Telephone Laboratories, Incorporated Electrically pulsed charge regenerator for semiconductor charge coupled devices
JPS5230180A (en) * 1975-09-02 1977-03-07 Matsushita Electric Ind Co Ltd Electric charge transmission unit
JPS52140239A (en) * 1976-05-19 1977-11-22 Nippon Telegr & Teleph Corp <Ntt> Electronic charge reproduction of electric charge coupling type shift regist er
US4139910A (en) * 1976-12-06 1979-02-13 International Business Machines Corporation Charge coupled device memory with method of doubled storage capacity and independent of process parameters and temperature
JPS5755174Y2 (US08124317-20120228-C00034.png) * 1977-06-03 1982-11-29
DE2808604A1 (de) * 1978-02-28 1979-08-30 Siemens Ag Aus ctd-leitungen bestehende koppelschaltung
US4152781A (en) * 1978-06-30 1979-05-01 International Business Machines Corporation Multiplexed and interlaced charge-coupled serial-parallel-serial memory device
US4165539A (en) * 1978-06-30 1979-08-21 International Business Machines Corporation Bidirectional serial-parallel-serial charge-coupled device
FR2436468A1 (fr) * 1978-09-15 1980-04-11 Thomson Csf Element de memoire dynamique a transfert de charges, et application notamment a un registre a decalage
JPH0584664U (ja) * 1991-04-16 1993-11-16 株式会社ユニー機工 収納容器
KR102538702B1 (ko) * 2018-04-23 2023-06-01 에스케이하이닉스 주식회사 반도체장치

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1810602B2 (de) * 1968-11-23 1978-11-16 Telefonbau Und Normalzeit Gmbh, 6000 Frankfurt Schaltungsanordnung fuer taktgesteuerte Umlaufspeicher,insbesondere fuer zeitmultiplex betriebene Fernsprechanlagen
US3670313A (en) * 1971-03-22 1972-06-13 Ibm Dynamically ordered magnetic bubble shift register memory

Also Published As

Publication number Publication date
FR2191208B1 (US08124317-20120228-C00034.png) 1976-06-18
JPS4959544A (US08124317-20120228-C00034.png) 1974-06-10
GB1386729A (en) 1975-03-12
FR2191208A1 (US08124317-20120228-C00034.png) 1974-02-01
DE2325922A1 (de) 1974-01-24
US3789247A (en) 1974-01-29
IT988995B (it) 1975-04-30
JPS532304B2 (US08124317-20120228-C00034.png) 1978-01-26
CA982238A (en) 1976-01-20

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Legal Events

Date Code Title Description
OD Request for examination
8128 New person/name/address of the agent

Representative=s name: GAUGEL, H., DIPL.-ING., PAT.-ASS., 7030 BOEBLINGEN

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee