DE2316118C3 - Verfahren zur Herstellung von Feldeffekttransistoren durch Anwendung einer selektiven Getterung - Google Patents

Verfahren zur Herstellung von Feldeffekttransistoren durch Anwendung einer selektiven Getterung

Info

Publication number
DE2316118C3
DE2316118C3 DE2316118A DE2316118A DE2316118C3 DE 2316118 C3 DE2316118 C3 DE 2316118C3 DE 2316118 A DE2316118 A DE 2316118A DE 2316118 A DE2316118 A DE 2316118A DE 2316118 C3 DE2316118 C3 DE 2316118C3
Authority
DE
Germany
Prior art keywords
layer
openings
gettering
areas
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2316118A
Other languages
German (de)
English (en)
Other versions
DE2316118A1 (de
DE2316118B2 (enExample
Inventor
Heinrich Dr. 8019 Ebersberg Schloetterer
Jenoe Dipl.-Phys. 8021 Neuried Tihanyi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE2316118A priority Critical patent/DE2316118C3/de
Priority to AT222874A priority patent/AT339378B/de
Priority to FR7409452A priority patent/FR2223839B1/fr
Priority to CH402574A priority patent/CH570041A5/xx
Priority to GB1331374A priority patent/GB1460489A/en
Priority to IT49646/74A priority patent/IT1003883B/it
Priority to NL7404256A priority patent/NL7404256A/xx
Priority to JP3508174A priority patent/JPS5648986B2/ja
Priority to LU69732A priority patent/LU69732A1/xx
Priority to US455589A priority patent/US3897625A/en
Priority to CA196,351A priority patent/CA991317A/en
Priority to SE7404271A priority patent/SE394767B/xx
Priority to BE142635A priority patent/BE813048A/xx
Publication of DE2316118A1 publication Critical patent/DE2316118A1/de
Publication of DE2316118B2 publication Critical patent/DE2316118B2/de
Application granted granted Critical
Publication of DE2316118C3 publication Critical patent/DE2316118C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/03—Manufacture or treatment wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/15—Silicon on sapphire SOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/913—Active solid-state devices, e.g. transistors, solid-state diodes with means to absorb or localize unwanted impurities or defects from semiconductors, e.g. heavy metal gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Bipolar Transistors (AREA)
DE2316118A 1973-03-30 1973-03-30 Verfahren zur Herstellung von Feldeffekttransistoren durch Anwendung einer selektiven Getterung Expired DE2316118C3 (de)

Priority Applications (13)

Application Number Priority Date Filing Date Title
DE2316118A DE2316118C3 (de) 1973-03-30 1973-03-30 Verfahren zur Herstellung von Feldeffekttransistoren durch Anwendung einer selektiven Getterung
AT222874A AT339378B (de) 1973-03-30 1974-03-18 Verfahren zur herstellung von feldeffekttransistoren durch anwendung einer selektiven getterung
FR7409452A FR2223839B1 (enExample) 1973-03-30 1974-03-20
CH402574A CH570041A5 (enExample) 1973-03-30 1974-03-22
IT49646/74A IT1003883B (it) 1973-03-30 1974-03-26 Procedimento per fabbricare transi stori a effetto di campo applicando un processo di assorbimento selet tivo
GB1331374A GB1460489A (en) 1973-03-30 1974-03-26 Field-effect transistors
NL7404256A NL7404256A (enExample) 1973-03-30 1974-03-28
JP3508174A JPS5648986B2 (enExample) 1973-03-30 1974-03-28
LU69732A LU69732A1 (enExample) 1973-03-30 1974-03-28
US455589A US3897625A (en) 1973-03-30 1974-03-28 Method for the production of field effect transistors by the application of selective gettering
CA196,351A CA991317A (en) 1973-03-30 1974-03-29 Method for the production of field effect transistors by the application of selective gettering
SE7404271A SE394767B (sv) 1973-03-30 1974-03-29 Forfarande for framstellning av felteffekttransistorer med ett kanalomrade med kort kanallengd
BE142635A BE813048A (fr) 1973-03-30 1974-03-29 Procede pour fabriquer des transistors a effet de champ en utilisant une getterisation selective

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2316118A DE2316118C3 (de) 1973-03-30 1973-03-30 Verfahren zur Herstellung von Feldeffekttransistoren durch Anwendung einer selektiven Getterung

Publications (3)

Publication Number Publication Date
DE2316118A1 DE2316118A1 (de) 1974-10-10
DE2316118B2 DE2316118B2 (enExample) 1975-04-03
DE2316118C3 true DE2316118C3 (de) 1975-11-27

Family

ID=5876584

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2316118A Expired DE2316118C3 (de) 1973-03-30 1973-03-30 Verfahren zur Herstellung von Feldeffekttransistoren durch Anwendung einer selektiven Getterung

Country Status (13)

Country Link
US (1) US3897625A (enExample)
JP (1) JPS5648986B2 (enExample)
AT (1) AT339378B (enExample)
BE (1) BE813048A (enExample)
CA (1) CA991317A (enExample)
CH (1) CH570041A5 (enExample)
DE (1) DE2316118C3 (enExample)
FR (1) FR2223839B1 (enExample)
GB (1) GB1460489A (enExample)
IT (1) IT1003883B (enExample)
LU (1) LU69732A1 (enExample)
NL (1) NL7404256A (enExample)
SE (1) SE394767B (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2801085A1 (de) * 1977-01-11 1978-07-13 Zaidan Hojin Handotai Kenkyu Statischer induktionstransistor
US4333224A (en) * 1978-04-24 1982-06-08 Buchanan Bobby L Method of fabricating polysilicon/silicon junction field effect transistors
US4380113A (en) * 1980-11-17 1983-04-19 Signetics Corporation Process for fabricating a high capacity memory cell
US4998146A (en) * 1989-05-24 1991-03-05 Xerox Corporation High voltage thin film transistor
FR2774509B1 (fr) * 1998-01-30 2001-11-16 Sgs Thomson Microelectronics Procede de depot d'une region de silicium monocristallin

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3490964A (en) * 1966-04-29 1970-01-20 Texas Instruments Inc Process of forming semiconductor devices by masking and diffusion
US3783052A (en) * 1972-11-10 1974-01-01 Motorola Inc Process for manufacturing integrated circuits on an alumina substrate
US3837071A (en) * 1973-01-16 1974-09-24 Rca Corp Method of simultaneously making a sigfet and a mosfet

Also Published As

Publication number Publication date
JPS5648986B2 (enExample) 1981-11-19
LU69732A1 (enExample) 1974-07-17
US3897625A (en) 1975-08-05
BE813048A (fr) 1974-07-15
GB1460489A (en) 1977-01-06
SE394767B (sv) 1977-07-04
FR2223839B1 (enExample) 1978-02-10
NL7404256A (enExample) 1974-10-02
CH570041A5 (enExample) 1975-11-28
IT1003883B (it) 1976-06-10
DE2316118A1 (de) 1974-10-10
FR2223839A1 (enExample) 1974-10-25
ATA222874A (de) 1977-02-15
AT339378B (de) 1977-10-10
CA991317A (en) 1976-06-15
DE2316118B2 (enExample) 1975-04-03
JPS49131082A (enExample) 1974-12-16

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
E77 Valid patent as to the heymanns-index 1977
8339 Ceased/non-payment of the annual fee