DE2027589A1 - Verfahren zur Herstellung von Transistoren - Google Patents

Verfahren zur Herstellung von Transistoren

Info

Publication number
DE2027589A1
DE2027589A1 DE19702027589 DE2027589A DE2027589A1 DE 2027589 A1 DE2027589 A1 DE 2027589A1 DE 19702027589 DE19702027589 DE 19702027589 DE 2027589 A DE2027589 A DE 2027589A DE 2027589 A1 DE2027589 A1 DE 2027589A1
Authority
DE
Germany
Prior art keywords
opening
phosphosilicate glass
coating
emitter
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19702027589
Other languages
German (de)
English (en)
Inventor
Martin Albert Somerville; Sonneborn Kurt Jaques Bound Brook; N.J. Blumenfeld (V.St.A.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of DE2027589A1 publication Critical patent/DE2027589A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/02129—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/003—Anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/144—Shallow diffusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Bipolar Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
DE19702027589 1969-06-05 1970-06-04 Verfahren zur Herstellung von Transistoren Pending DE2027589A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US83082269A 1969-06-05 1969-06-05

Publications (1)

Publication Number Publication Date
DE2027589A1 true DE2027589A1 (de) 1970-12-10

Family

ID=25257756

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19702027589 Pending DE2027589A1 (de) 1969-06-05 1970-06-04 Verfahren zur Herstellung von Transistoren

Country Status (7)

Country Link
US (1) US3615942A (enExample)
JP (1) JPS4838098B1 (enExample)
DE (1) DE2027589A1 (enExample)
FR (1) FR2045816B1 (enExample)
GB (1) GB1317331A (enExample)
NL (1) NL7008144A (enExample)
SE (1) SE362537B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755015A (en) * 1971-12-10 1973-08-28 Gen Electric Anti-reflection coating for semiconductor diode array targets
US3839104A (en) * 1972-08-31 1974-10-01 Texas Instruments Inc Fabrication technique for high performance semiconductor devices
US3943015A (en) * 1973-06-29 1976-03-09 International Business Machines Corporation Method for high temperature semiconductor processing
JPS5266377A (en) * 1975-11-29 1977-06-01 Toshiba Corp Manufacture of semiconductor device
JPS5279777A (en) * 1975-12-26 1977-07-05 Toshiba Corp Production of semiconductor device
JPS5530846A (en) * 1978-08-28 1980-03-04 Hitachi Ltd Method for manufacturing fixed memory
JPS5534444A (en) * 1978-08-31 1980-03-11 Fujitsu Ltd Preparation of semiconductor device
NL8701357A (nl) * 1987-06-11 1989-01-02 Philips Nv Halfgeleiderinrichting bevattende een condensator en een begraven passiveringslaag.
HK1048889A1 (zh) * 1999-06-28 2003-04-17 尤纳克西斯巴尔策斯公司 部件及其制造方法
US6582633B2 (en) 2001-01-17 2003-06-24 Akzo Nobel N.V. Process for producing objects
SG10202010798QA (en) * 2019-11-08 2021-06-29 Tokyo Electron Ltd Etching method and plasma processing apparatus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1283400B (de) * 1965-11-23 1968-11-21 Siemens Ag Verfahren zum Herstellen einer Vielzahl von Siliciumplanartransistoren
FR1516618A (fr) * 1966-03-23 1968-03-08 Matsushita Electronics Corp Procédé pour la fabrication d'un élément semi-conducteur
US3497407A (en) * 1966-12-28 1970-02-24 Ibm Etching of semiconductor coatings of sio2

Also Published As

Publication number Publication date
FR2045816B1 (enExample) 1975-02-21
US3615942A (en) 1971-10-26
FR2045816A1 (enExample) 1971-03-05
GB1317331A (en) 1973-05-16
JPS4838098B1 (enExample) 1973-11-15
NL7008144A (enExample) 1970-12-08
SE362537B (enExample) 1973-12-10

Similar Documents

Publication Publication Date Title
EP0010596B1 (de) Verfahren zur Ausbildung von Maskenöffnungen bei der Herstellung von Halbleiteranordnungen
EP0036634B1 (de) Verfahren zur Herstellung einer bipolaren Transistorstruktur
DE2618445C2 (de) Verfahren zum Herstellen eines bipolaren Transistors
DE2729171C2 (de) Verfahren zur Herstellung einer integrierten Schaltung
DE2462644C2 (de) Verfahren zur Herstellung eines Transistors
EP0001586B1 (de) Integrierte Halbleiteranordnung mit vertikalen NPN- und PNP-Strukturen und Verfahren zur Herstellung
DE2928923C2 (enExample)
DE1298633B (de) Halbleiterkoerper fuer integrierte Halbleiterschaltungen
CH615781A5 (enExample)
DE2744059A1 (de) Verfahren zur gemeinsamen integrierten herstellung von feldeffekt- und bipolar-transistoren
EP0006510B1 (de) Verfahren zum Erzeugen aneinander grenzender, unterschiedlich dotierter Siliciumbereiche
DE2103468C3 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE2027589A1 (de) Verfahren zur Herstellung von Transistoren
DE2633714C2 (de) Integrierte Halbleiter-Schaltungsanordnung mit einem bipolaren Transistor und Verfahren zu ihrer Herstellung
DE2718449A1 (de) Verfahren zur herstellung einer halbleiteranordnung und durch dieses verfahren hergestellte anordnung
DE2207264A1 (de) Halbleiterschaltung mit drei Anschlußebenen und Verfahren zu ihrer Herstellung.
DE2534132C3 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE2152298A1 (de) Verfahren zur Herstellung von Feldeffekt-und bipolaren Transistoreinrichtungen
DE2617482A1 (de) Verfahren zur dielektrischen isolation integrierter halbleiteranordnungen
DE2904480B2 (de) Integrierte Halbleiterschaltung und Verfahren zu ihrem Herstellen
DE2027588A1 (de) Verfahren zur Herstellung von mit Phosphorsihkatglas passivierten Transistoren
DE2600375C3 (de) Halbleiteranordnung mit mindestens zwei komplementären Transistoren und Verfahren zu ihrer Herstellung
DE2320420A1 (de) Verfahren zur herstellung eines leitfaehigen verbindungsmusters auf halbleiterschaltungen sowie nach dem verfahren hergestellte anordnungen
DE2537327A1 (de) Halbleiterbauelement mit einem pn- uebergang gleichfoermiger stromdichteverteilung und verfahren zum herstellen eines solchen halbleiterbauelements
DE2510951C3 (de) Verfahren zur Herstellung einer monolithisch integrierten Halbleiterschaltung

Legal Events

Date Code Title Description
OHJ Non-payment of the annual fee