DE1962018A1 - Verfahren zum AEtzen zusammengesetzter Schichtkoerper - Google Patents

Verfahren zum AEtzen zusammengesetzter Schichtkoerper

Info

Publication number
DE1962018A1
DE1962018A1 DE19691962018 DE1962018A DE1962018A1 DE 1962018 A1 DE1962018 A1 DE 1962018A1 DE 19691962018 DE19691962018 DE 19691962018 DE 1962018 A DE1962018 A DE 1962018A DE 1962018 A1 DE1962018 A1 DE 1962018A1
Authority
DE
Germany
Prior art keywords
layer
etching
solution
silicon nitride
concentration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19691962018
Other languages
German (de)
English (en)
Inventor
Carlson Harold Gary
Victor Harrap
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE1962018A1 publication Critical patent/DE1962018A1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Landscapes

  • Weting (AREA)
  • Silicon Compounds (AREA)
DE19691962018 1968-12-30 1969-12-11 Verfahren zum AEtzen zusammengesetzter Schichtkoerper Pending DE1962018A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US78773868A 1968-12-30 1968-12-30

Publications (1)

Publication Number Publication Date
DE1962018A1 true DE1962018A1 (de) 1970-07-09

Family

ID=25142391

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19691962018 Pending DE1962018A1 (de) 1968-12-30 1969-12-11 Verfahren zum AEtzen zusammengesetzter Schichtkoerper

Country Status (6)

Country Link
US (1) US3607480A (https=)
JP (1) JPS4940844B1 (https=)
DE (1) DE1962018A1 (https=)
FR (1) FR2027318A1 (https=)
GB (1) GB1265038A (https=)
NL (1) NL6918927A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3343704A1 (de) * 1983-12-02 1985-06-13 Siemens AG, 1000 Berlin und 8000 München Verfahren und vorrichtung zum aetzen von lochrasterplatten, insbesondere fuer plasma-kathoden-display

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3979241A (en) * 1968-12-28 1976-09-07 Fujitsu Ltd. Method of etching films of silicon nitride and silicon dioxide
US3913214A (en) * 1970-05-05 1975-10-21 Licentia Gmbh Method of producing a semiconductor device
US3694700A (en) * 1971-02-19 1972-09-26 Nasa Integrated circuit including field effect transistor and cerment resistor
US3842490A (en) * 1971-04-21 1974-10-22 Signetics Corp Semiconductor structure with sloped side walls and method
US3859222A (en) * 1971-07-19 1975-01-07 North American Rockwell Silicon nitride-silicon oxide etchant
US3860466A (en) * 1971-10-22 1975-01-14 Texas Instruments Inc Nitride composed masking for integrated circuits
US3808069A (en) * 1972-03-15 1974-04-30 Bell Telephone Labor Inc Forming windows in composite dielectric layers
US4029542A (en) * 1975-09-19 1977-06-14 Rca Corporation Method for sloping the sidewalls of multilayer P+ PN+ junction mesa structures
JPS5334484A (en) * 1976-09-10 1978-03-31 Toshiba Corp Forming method for multi layer wiring
US4092211A (en) * 1976-11-18 1978-05-30 Northern Telecom Limited Control of etch rate of silicon dioxide in boiling phosphoric acid
NL7706802A (nl) * 1977-06-21 1978-12-27 Philips Nv Werkwijze voor het vervaardigen van een half- geleiderinrichting en halfgeleiderinrichting vervaardigd met behulp van de werkwijze.
US4269654A (en) * 1977-11-18 1981-05-26 Rca Corporation Silicon nitride and silicon oxide etchant
US4254161A (en) * 1979-08-16 1981-03-03 International Business Machines Corporation Prevention of low pressure chemical vapor deposition silicon dioxide undercutting and flaking
US5043224A (en) * 1988-05-12 1991-08-27 Lehigh University Chemically enhanced thermal oxidation and nitridation of silicon and products thereof
EP0375255A3 (en) * 1988-12-21 1991-09-04 AT&T Corp. Method for reducing mobile ion contamination in semiconductor integrated circuits
US5198298A (en) * 1989-10-24 1993-03-30 Advanced Micro Devices, Inc. Etch stop layer using polymers
US5114532A (en) * 1991-03-21 1992-05-19 Seagate Technology, Inc. Process of etching iron-silicon-aluminum trialloys and etchant solutions used therefor
US5057450A (en) * 1991-04-01 1991-10-15 International Business Machines Corporation Method for fabricating silicon-on-insulator structures
US6048406A (en) * 1997-04-08 2000-04-11 Texas Instruments Incorporated Benign method for etching silicon dioxide
US6287983B2 (en) * 1997-12-31 2001-09-11 Texas Instruments Incorporated Selective nitride etching with silicate ion pre-loading
US6037271A (en) * 1998-10-21 2000-03-14 Fsi International, Inc. Low haze wafer treatment process
KR100867086B1 (ko) * 2001-04-27 2008-11-04 엔엑스피 비 브이 반도체 장치 제조 방법 및 장치
US6835667B2 (en) * 2002-06-14 2004-12-28 Fsi International, Inc. Method for etching high-k films in solutions comprising dilute fluoride species
US8778210B2 (en) * 2006-12-21 2014-07-15 Advanced Technology Materials, Inc. Compositions and methods for the selective removal of silicon nitride
KR20080079999A (ko) * 2007-02-28 2008-09-02 토소가부시키가이샤 에칭 방법 및 그것에 이용되는 에칭용 조성물
DE102007030957A1 (de) * 2007-07-04 2009-01-08 Siltronic Ag Verfahren zum Reinigen einer Halbleiterscheibe mit einer Reinigungslösung
EP2463410B1 (en) * 2010-12-13 2018-07-04 Rohm and Haas Electronic Materials LLC Electrochemical etching of semiconductors
CN102244149A (zh) * 2011-07-20 2011-11-16 苏州阿特斯阳光电力科技有限公司 一种硅太阳能电池扩散死层的去除方法
CN104395991B (zh) * 2012-06-29 2017-06-20 株式会社半导体能源研究所 半导体装置
WO2020203697A1 (ja) * 2019-03-29 2020-10-08 デンカ株式会社 窒化ケイ素粉末及びその製造方法、並びに窒化ケイ素焼結体の製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3343704A1 (de) * 1983-12-02 1985-06-13 Siemens AG, 1000 Berlin und 8000 München Verfahren und vorrichtung zum aetzen von lochrasterplatten, insbesondere fuer plasma-kathoden-display

Also Published As

Publication number Publication date
FR2027318A1 (https=) 1970-09-25
JPS4940844B1 (https=) 1974-11-06
GB1265038A (https=) 1972-03-01
US3607480A (en) 1971-09-21
NL6918927A (https=) 1970-07-02

Similar Documents

Publication Publication Date Title
DE1962018A1 (de) Verfahren zum AEtzen zusammengesetzter Schichtkoerper
EP0000897B1 (de) Verfahren zum Herstellen von lateral isolierten Siliciumbereichen
DE1614540A1 (de) Halbleiteranordnung
EP0008359A2 (de) Verfahren zum Herstellen einer Dünnfilmstruktur
DE2400670A1 (de) Verfahren zur herstellung von mostransistoren
WO1997004319A1 (de) Verfahren zur herstellung von beschleunigungssensoren
DE1621477B2 (de) Waessrige aetzloesung zum selektiven aetzen von silicium dioxid und phosphatglasschichten auf halbleiterkoerpern und verwendung der loesung zur reinigenden aetzung von halbleiterkoerpern
DE3132905A1 (de) "verfahren zur herstellung einer halbleiteranordnung"
DE2641752A1 (de) Verfahren zur herstellung eines feldeffekttransistors
DE19654791B4 (de) Verfahren und Vorrichtung zum Trennen einer Halbleiterschicht von einem Substrat
DE1961634A1 (de) Verfahren zur Herstellung eines Misfet
DE2654979C3 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE1814029B2 (de) Erzeugung einkristalliner und polykristalliner halbleiterbereiche auf einem inkristallinen halbleitersubstrat
DE3434727A1 (de) Verfahren zur herstellung von siliciumcarbid(sic)-metalloxidhalbleiter-(mos)-bauteilen
DE2239687B2 (de) Verfahren zum aetzen eines mehrschichtigen halbleiterkoerpers mit einem fluessigen aetzmittel
EP0053711A2 (de) Verfahren zum Herstellen von Strukturen von aus Siliziden oder aus Silizid-Polysilizium bestehenden Schichten durch reaktives Sputterätzen
DE2451486A1 (de) Verfahren zum herstellen kleinster oeffnungen in integrierten schaltungen
DE3318001A1 (de) Verfahren zum stromlosen abscheiden von platin auf silicium
DE10306310A1 (de) Dual-Gateoxid-Verfahren ohne kritischen Resist und ohne N¶2¶-Implantierung
EP1360143A2 (de) Verfahren zum erzeugen von oberflächenmikromechanikstrukturen und sensor
DE2807475A1 (de) Phosphor und stickstoff enthaltendes material, seine herstellung und verwendung
DE3424329A1 (de) Verfahren zum herstellen von masshaltigen titanstrukturen
DE1614358C3 (de) Verfahren zum Herstellen einer Ätzmaske für die Ätzbehandlung von Halbleiterkörpern
DE1614135C2 (de) Verfahren zum Herstellen eines aus zwei übereinanderliegenden Siliciumdioxid-Schichten unterschiedlicher Ätzbarkeit in ein und demselben Ätzmittel bestehenden Ätzmaske hoher Genauigkeit
DE4415567B4 (de) Verfahren zur Erzeugung einer SOI-Struktur mit einer Isolationsschicht auf einem Siliziumwafer und einer darauf epitaktisch aufgebrachten Siliziumschicht