DE1805707B2 - Verfahren zum herstellen von halbleiteranordnungen - Google Patents

Verfahren zum herstellen von halbleiteranordnungen

Info

Publication number
DE1805707B2
DE1805707B2 DE19681805707 DE1805707A DE1805707B2 DE 1805707 B2 DE1805707 B2 DE 1805707B2 DE 19681805707 DE19681805707 DE 19681805707 DE 1805707 A DE1805707 A DE 1805707A DE 1805707 B2 DE1805707 B2 DE 1805707B2
Authority
DE
Germany
Prior art keywords
nitride
semiconductor
film
silicon
crystal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE19681805707
Other languages
German (de)
English (en)
Other versions
DE1805707A1 (de
Inventor
Takichi Tokio Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Publication of DE1805707A1 publication Critical patent/DE1805707A1/de
Publication of DE1805707B2 publication Critical patent/DE1805707B2/de
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
DE19681805707 1967-10-28 1968-10-28 Verfahren zum herstellen von halbleiteranordnungen Pending DE1805707B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6900167 1967-10-28

Publications (2)

Publication Number Publication Date
DE1805707A1 DE1805707A1 (de) 1969-08-21
DE1805707B2 true DE1805707B2 (de) 1972-03-16

Family

ID=13389909

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19681805707 Pending DE1805707B2 (de) 1967-10-28 1968-10-28 Verfahren zum herstellen von halbleiteranordnungen

Country Status (4)

Country Link
DE (1) DE1805707B2 (US06252093-20010626-C00008.png)
FR (1) FR1594694A (US06252093-20010626-C00008.png)
GB (1) GB1205320A (US06252093-20010626-C00008.png)
NL (1) NL6815286A (US06252093-20010626-C00008.png)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL159817B (nl) * 1966-10-05 1979-03-15 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting.
GB1332931A (en) * 1970-01-15 1973-10-10 Mullard Ltd Methods of manufacturing a semiconductor device
US4002511A (en) * 1975-04-16 1977-01-11 Ibm Corporation Method for forming masks comprising silicon nitride and novel mask structures produced thereby
IT1080473B (it) * 1977-07-25 1985-05-16 Ducati Elettrotecnica Spa Condensatore elettrico autorigene rante con dielettrico misto
GB2042801B (en) * 1979-02-13 1983-12-14 Standard Telephones Cables Ltd Contacting semicnductor devices
JPS5955052A (ja) * 1982-09-24 1984-03-29 Hitachi Ltd 半導体集積回路装置の製造方法
DE3312076A1 (de) * 1983-04-02 1984-10-04 O.D.A.M. - Office de Distribution d'Appareils Médicaux, Wissembourg Kondensator hoher energiedichte und verfahren zu seiner herstellung

Also Published As

Publication number Publication date
FR1594694A (US06252093-20010626-C00008.png) 1970-07-17
DE1805707A1 (de) 1969-08-21
NL6815286A (US06252093-20010626-C00008.png) 1969-05-01
GB1205320A (en) 1970-09-16

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