DE1261487B - Verfahren zur Herstellung eines Siliciumkoerpers mit mehreren Schichten verschiedenen Leitungstyps - Google Patents

Verfahren zur Herstellung eines Siliciumkoerpers mit mehreren Schichten verschiedenen Leitungstyps

Info

Publication number
DE1261487B
DE1261487B DET16907A DET0016907A DE1261487B DE 1261487 B DE1261487 B DE 1261487B DE T16907 A DET16907 A DE T16907A DE T0016907 A DET0016907 A DE T0016907A DE 1261487 B DE1261487 B DE 1261487B
Authority
DE
Germany
Prior art keywords
silicon body
layer
conductivity type
exposed
vapors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DET16907A
Other languages
German (de)
English (en)
Inventor
Boyd Cornelison
Elmer Albert Wolff Jun
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE1261487B publication Critical patent/DE1261487B/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B31/00—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor
    • C30B31/06—Diffusion or doping processes for single crystals or homogeneous polycrystalline material with defined structure; Apparatus therefor by contacting with diffusion material in the gaseous state
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/834—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge further characterised by the dopants
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/919—Compensation doping

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • Materials Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
DET16907A 1958-07-09 1959-07-08 Verfahren zur Herstellung eines Siliciumkoerpers mit mehreren Schichten verschiedenen Leitungstyps Pending DE1261487B (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US747457A US2979429A (en) 1958-07-09 1958-07-09 Diffused transistor and method of making

Publications (1)

Publication Number Publication Date
DE1261487B true DE1261487B (de) 1968-02-22

Family

ID=25005137

Family Applications (1)

Application Number Title Priority Date Filing Date
DET16907A Pending DE1261487B (de) 1958-07-09 1959-07-08 Verfahren zur Herstellung eines Siliciumkoerpers mit mehreren Schichten verschiedenen Leitungstyps

Country Status (6)

Country Link
US (1) US2979429A (enExample)
CH (1) CH375799A (enExample)
DE (1) DE1261487B (enExample)
FR (1) FR1241150A (enExample)
GB (1) GB861038A (enExample)
NL (1) NL241124A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3430009A1 (de) * 1984-05-18 1985-11-21 Mitel Corp., Kanata, Ontario Verfahren und vorrichtung zum dotieren von halbleitersubstraten

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3215571A (en) * 1962-10-01 1965-11-02 Bell Telephone Labor Inc Fabrication of semiconductor bodies
US3362858A (en) * 1963-01-04 1968-01-09 Westinghouse Electric Corp Fabrication of semiconductor controlled rectifiers
US3123532A (en) * 1963-03-06 1964-03-03 Certificate of correction
US3943016A (en) * 1970-12-07 1976-03-09 General Electric Company Gallium-phosphorus simultaneous diffusion process

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2802760A (en) * 1955-12-02 1957-08-13 Bell Telephone Labor Inc Oxidation of semiconductive surfaces for controlled diffusion
US2827403A (en) * 1956-08-06 1958-03-18 Pacific Semiconductors Inc Method for diffusing active impurities into semiconductor materials

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE547274A (enExample) * 1955-06-20

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2802760A (en) * 1955-12-02 1957-08-13 Bell Telephone Labor Inc Oxidation of semiconductive surfaces for controlled diffusion
US2827403A (en) * 1956-08-06 1958-03-18 Pacific Semiconductors Inc Method for diffusing active impurities into semiconductor materials

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3430009A1 (de) * 1984-05-18 1985-11-21 Mitel Corp., Kanata, Ontario Verfahren und vorrichtung zum dotieren von halbleitersubstraten

Also Published As

Publication number Publication date
NL241124A (enExample)
CH375799A (de) 1964-03-15
FR1241150A (fr) 1960-09-16
US2979429A (en) 1961-04-11
GB861038A (en) 1961-02-15

Similar Documents

Publication Publication Date Title
DE2823967C2 (enExample)
DE3002051A1 (de) Verfahren zur herstellung von komplementaeren mos-transistoren hoher integration fuer hohe spannungen
DE1246890B (de) Diffusionsverfahren zum Herstellen eines Halbleiterbauelements
EP0852062B1 (de) Dotierverfahren zur herstellung von homoübergängen in halbleitersubstraten
DE1489258B1 (de) Verfahren zum Herstellen einer duennen leitenden Zone unter der Oberflaeche eines Siliciumkoerpers
DE1087704B (de) Verfahren zur Herstellung von Halbleiteranordnungen mit wenigstens einem p-n-UEbergang
DE1614852B2 (de) Verfahren zur Herstellung einer integrierten Halbleiterschaltung mit einem NPN-Transistor, einem PNP-Transistor und weiteren Schaltungselementen
DE1261487B (de) Verfahren zur Herstellung eines Siliciumkoerpers mit mehreren Schichten verschiedenen Leitungstyps
DE2154386C3 (de) Verfahren zum Herstellen einer epitaktischen Halbleiterschicht auf einem Halbleitersubstrat durch Abscheiden aus einem Reaktionsgas/Trägergas-Gemisch
DE3039009C2 (de) Sperrschicht-Feldeffekttransistor
DE69023582T2 (de) Verfahren zur Herstellung eines Halbleiterelementes mittels Ionen-Implantation.
DE2019450C3 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE1544323A1 (de) Verfahren zur Erzeugung von p-Diffusionen in Germanium und zur Herstellung doppelt diffundierter planarer Germaniumtransistoren
DE1218618B (de) Diffusionsverfahren zum Herstellen eines Transistors
DE1174910B (de) Verfahren zur Herstellung eines Transistors
DE1769271C3 (de) Verfahren zum Herstellen einer Festkörperschaltung
DE2541161A1 (de) Verfahren zur herstellung monolithischer komplementaerer transistoren
DE2131993C2 (de) Verfahren zum Herstellen eines niederohmigen Anschlusses
DE1639055B1 (de) Verfahren zum herstellen einer halbleiteranordnung und danach hergestellte halbleiteranordnung
DE2356109B2 (de) Verfahren zur Herstellung eines HF-Planartransistors
DE1564106B2 (de) Verfahren zum herstellen eines feldeffekttransistorelementes
DE1544325A1 (de) Verfahren zur Bildung flacher Diffusionsbereiche in Galliumarsenid
DE1614286C3 (de) Halbleiteranordnung und Verfahren zu ihrer Herstellung
DE2039255A1 (de) Ohmsche Kontakte auf planaren Halbleiterbauelementen und Verfahren zu ihrer Herstellung
DE2018448A1 (de) Verfahren zum Herstellen einer integrierten Schaltungsanordnung