DE1132968B - Schaltung zur Bildung der íÀOder-AberíÂ-Funktion aus zwei Eingangssignalen - Google Patents
Schaltung zur Bildung der íÀOder-AberíÂ-Funktion aus zwei EingangssignalenInfo
- Publication number
- DE1132968B DE1132968B DEJ19725A DEJ0019725A DE1132968B DE 1132968 B DE1132968 B DE 1132968B DE J19725 A DEJ19725 A DE J19725A DE J0019725 A DEJ0019725 A DE J0019725A DE 1132968 B DE1132968 B DE 1132968B
- Authority
- DE
- Germany
- Prior art keywords
- block
- voltage
- output
- transistor
- transistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003247 decreasing effect Effects 0.000 claims 1
- 230000000295 complement effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000012905 input function Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004513 sizing Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/502—Half adders; Full adders consisting of two cascaded half adders
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0002—Multistate logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/0823—Multistate logic
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
- H03K19/086—Emitter coupled logic
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Theoretical Computer Science (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Optimization (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US22179A US2994852A (en) | 1960-04-14 | 1960-04-14 | Decoding circuit |
| US22289A US3099753A (en) | 1960-04-14 | 1960-04-14 | Three level logical circuits |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE1132968B true DE1132968B (de) | 1962-07-12 |
Family
ID=26695626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DEJ19725A Pending DE1132968B (de) | 1960-04-14 | 1961-04-11 | Schaltung zur Bildung der íÀOder-AberíÂ-Funktion aus zwei Eingangssignalen |
Country Status (5)
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3210528A (en) * | 1962-06-18 | 1965-10-05 | Magill | Binary coded ternary computer system |
| US3508033A (en) * | 1967-01-17 | 1970-04-21 | Rca Corp | Counter circuits |
| US3628000A (en) * | 1968-04-18 | 1971-12-14 | Ibm | Data handling devices for radix {37 n{30 2{38 {0 operation |
| US4494017A (en) * | 1982-03-29 | 1985-01-15 | International Business Machines Corporation | Complementary decode circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| NL195088A (US07345094-20080318-C00003.png) * | 1954-02-26 | |||
| GB789166A (en) * | 1954-11-15 | 1958-01-15 | Ncr Co | Improvements in or relating to electronic arithmetic units |
| US3015734A (en) * | 1956-10-18 | 1962-01-02 | Navigation Computer Corp | Transistor computer circuit |
| US2898479A (en) * | 1957-06-28 | 1959-08-04 | Hughes Aircraft Co | Clock pulse circuit for transistor flip-flop |
| US2966305A (en) * | 1957-08-16 | 1960-12-27 | Ibm | Simultaneous carry adder |
| US2870348A (en) * | 1957-12-16 | 1959-01-20 | Ibm | System for selectively energizing one of three circuits responsive to variation of two conditions |
-
1960
- 1960-04-14 US US22289A patent/US3099753A/en not_active Expired - Lifetime
- 1960-04-14 US US22179A patent/US2994852A/en not_active Expired - Lifetime
-
1961
- 1961-01-13 FR FR849612A patent/FR1278866A/fr not_active Expired
- 1961-04-11 DE DEJ19725A patent/DE1132968B/de active Pending
- 1961-04-13 FR FR79583D patent/FR79583E/fr not_active Expired
- 1961-04-14 GB GB13459/61A patent/GB935221A/en not_active Expired
- 1961-04-14 NL NL263602D patent/NL263602A/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| NL263602A (US07345094-20080318-C00003.png) | 1964-05-25 |
| FR1278866A (fr) | 1961-12-15 |
| GB935221A (en) | 1963-08-28 |
| US2994852A (en) | 1961-08-01 |
| US3099753A (en) | 1963-07-30 |
| FR79583E (US07345094-20080318-C00003.png) | 1963-03-29 |
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