DE112022004775T5 - Verfahren zur Herstellung einer Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung einer Halbleitervorrichtung Download PDF

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Publication number
DE112022004775T5
DE112022004775T5 DE112022004775.5T DE112022004775T DE112022004775T5 DE 112022004775 T5 DE112022004775 T5 DE 112022004775T5 DE 112022004775 T DE112022004775 T DE 112022004775T DE 112022004775 T5 DE112022004775 T5 DE 112022004775T5
Authority
DE
Germany
Prior art keywords
wafer
source
main surface
electrode
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE112022004775.5T
Other languages
German (de)
English (en)
Inventor
Yuki Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of DE112022004775T5 publication Critical patent/DE112022004775T5/de
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/60—Schottky-barrier diodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/11—Separation of active layers from substrates
    • H10P95/112—Separation of active layers from substrates leaving a reusable substrate, e.g. epitaxial lift off
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01331—Manufacture or treatment of die-attach connectors using blanket deposition
    • H10W72/01333—Manufacture or treatment of die-attach connectors using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating
    • H10W72/01335—Manufacture or treatment of die-attach connectors using blanket deposition in liquid form, e.g. spin coating, spray coating or immersion coating by plating, e.g. electroless plating or electroplating

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  • Electrodes Of Semiconductors (AREA)
DE112022004775.5T 2021-11-05 2022-10-28 Verfahren zur Herstellung einer Halbleitervorrichtung Pending DE112022004775T5 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2021-181322 2021-11-05
JP2021181322 2021-11-05
PCT/JP2022/040503 WO2023080091A1 (ja) 2021-11-05 2022-10-28 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE112022004775T5 true DE112022004775T5 (de) 2024-09-05

Family

ID=86241070

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112022004775.5T Pending DE112022004775T5 (de) 2021-11-05 2022-10-28 Verfahren zur Herstellung einer Halbleitervorrichtung

Country Status (5)

Country Link
US (1) US20240282634A1 (https=)
JP (1) JPWO2023080091A1 (https=)
CN (1) CN118202445A (https=)
DE (1) DE112022004775T5 (https=)
WO (1) WO2023080091A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025224813A1 (ja) * 2024-04-23 2025-10-30 三菱電機株式会社 半導体装置及び半導体装置の製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021181322A (ja) 2020-05-18 2021-11-25 川上産業株式会社 気泡シート、気泡シートの製造装置、気泡シートの製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001144123A (ja) * 1999-09-02 2001-05-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
CN110785833A (zh) * 2017-06-19 2020-02-11 罗姆股份有限公司 半导体装置的制造方法及晶片粘合结构体
WO2021019697A1 (ja) * 2019-07-30 2021-02-04 昭和電工マテリアルズ株式会社 電子部品装置を製造する方法、及び電子部品装置
JP7259795B2 (ja) * 2020-03-31 2023-04-18 株式会社デンソー 炭化珪素ウェハの製造方法、半導体基板の製造方法および炭化珪素半導体装置の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021181322A (ja) 2020-05-18 2021-11-25 川上産業株式会社 気泡シート、気泡シートの製造装置、気泡シートの製造方法

Also Published As

Publication number Publication date
US20240282634A1 (en) 2024-08-22
WO2023080091A1 (ja) 2023-05-11
JPWO2023080091A1 (https=) 2023-05-11
CN118202445A (zh) 2024-06-14

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R079 Amendment of ipc main class

Free format text: PREVIOUS MAIN CLASS: H01L0021304000

Ipc: H10P0054300000