DE112020002205B4 - Halbleitervorrichtung und Herstellungsverfahren einer Halbleitervorrichtung - Google Patents

Halbleitervorrichtung und Herstellungsverfahren einer Halbleitervorrichtung Download PDF

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DE112020002205B4
DE112020002205B4 DE112020002205.6T DE112020002205T DE112020002205B4 DE 112020002205 B4 DE112020002205 B4 DE 112020002205B4 DE 112020002205 T DE112020002205 T DE 112020002205T DE 112020002205 B4 DE112020002205 B4 DE 112020002205B4
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semiconductor substrate
hydrogen
chemical
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DE112020002205T5 (de
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Kosuke YOSHIDA
Takashi Yoshimura
Hiroshi TAKISHITA
Misaki Uchida
Michio Nemoto
Nao SUGANUMA
Motoyoshi KUBOUCHI
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Fuji Electric Co Ltd
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    • H10P30/20Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
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    • H10D12/031Manufacture or treatment of IGBTs
    • H10D12/032Manufacture or treatment of IGBTs of vertical IGBTs
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    • H10D12/441Vertical IGBTs
    • H10D12/461Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H10D12/481Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
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    • H10D62/103Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)
DE112020002205.6T 2019-12-18 2020-12-10 Halbleitervorrichtung und Herstellungsverfahren einer Halbleitervorrichtung Active DE112020002205B4 (de)

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JP2019228409 2019-12-18
JP2019-228409 2019-12-18
JP2020087349 2020-05-19
JP2020-087349 2020-05-19
JP2020-189026 2020-11-12
JP2020189026 2020-11-12
PCT/JP2020/046167 WO2021125064A1 (ja) 2019-12-18 2020-12-10 半導体装置および半導体装置の製造方法

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DE112020002205B4 true DE112020002205B4 (de) 2025-06-05

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US (2) US12119227B2 (https=)
JP (3) JP7215599B2 (https=)
CN (1) CN113892184B (https=)
DE (1) DE112020002205B4 (https=)
WO (1) WO2021125064A1 (https=)

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JP7361634B2 (ja) * 2020-03-02 2023-10-16 三菱電機株式会社 半導体装置及び半導体装置の製造方法
JP7848459B2 (ja) 2021-10-15 2026-04-21 富士電機株式会社 解析方法、プログラムおよび半導体装置の製造方法
JP7652341B2 (ja) * 2022-05-30 2025-03-27 富士電機株式会社 半導体装置の製造方法
JP7672366B2 (ja) * 2022-06-27 2025-05-07 三菱電機株式会社 半導体装置
JP2024014333A (ja) * 2022-07-22 2024-02-01 富士電機株式会社 半導体装置および半導体装置の製造方法
JP7831641B2 (ja) * 2022-12-13 2026-03-17 富士電機株式会社 半導体装置および半導体装置の製造方法
JP2024107868A (ja) * 2023-01-30 2024-08-09 株式会社デンソー 半導体装置
JPWO2025028573A1 (https=) * 2023-08-01 2025-02-06
WO2025084305A1 (ja) * 2023-10-17 2025-04-24 富士電機株式会社 半導体基板の評価方法および半導体装置の製造方法

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