DE10205559B4 - Integrierte Schaltung und Verfahren und Vorrichtung zum Entwurf einer integrierten Schaltung - Google Patents

Integrierte Schaltung und Verfahren und Vorrichtung zum Entwurf einer integrierten Schaltung Download PDF

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Publication number
DE10205559B4
DE10205559B4 DE10205559A DE10205559A DE10205559B4 DE 10205559 B4 DE10205559 B4 DE 10205559B4 DE 10205559 A DE10205559 A DE 10205559A DE 10205559 A DE10205559 A DE 10205559A DE 10205559 B4 DE10205559 B4 DE 10205559B4
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DE
Germany
Prior art keywords
connections
connection
integrated circuit
capacity
miller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10205559A
Other languages
German (de)
English (en)
Other versions
DE10205559A1 (de
Inventor
Brian C. Fort Collins Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avago Technologies International Sales Pte Ltd
Original Assignee
Avago Technologies General IP Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Avago Technologies General IP Singapore Pte Ltd filed Critical Avago Technologies General IP Singapore Pte Ltd
Publication of DE10205559A1 publication Critical patent/DE10205559A1/de
Application granted granted Critical
Publication of DE10205559B4 publication Critical patent/DE10205559B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE10205559A 2001-02-14 2002-02-11 Integrierte Schaltung und Verfahren und Vorrichtung zum Entwurf einer integrierten Schaltung Expired - Fee Related DE10205559B4 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/783,434 US6567966B2 (en) 2001-02-14 2001-02-14 Interweaved integrated circuit interconnects
US09/783,434 2001-02-14

Publications (2)

Publication Number Publication Date
DE10205559A1 DE10205559A1 (de) 2002-08-29
DE10205559B4 true DE10205559B4 (de) 2007-05-10

Family

ID=25129237

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10205559A Expired - Fee Related DE10205559B4 (de) 2001-02-14 2002-02-11 Integrierte Schaltung und Verfahren und Vorrichtung zum Entwurf einer integrierten Schaltung

Country Status (3)

Country Link
US (1) US6567966B2 (https=)
JP (1) JP2002318827A (https=)
DE (1) DE10205559B4 (https=)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7103863B2 (en) * 2001-06-08 2006-09-05 Magma Design Automation, Inc. Representing the design of a sub-module in a hierarchical integrated circuit design and analysis system
US6640331B2 (en) * 2001-11-29 2003-10-28 Sun Microsystems, Inc. Decoupling capacitor assignment technique with respect to leakage power
US6938234B1 (en) * 2002-01-22 2005-08-30 Cadence Design Systems, Inc. Method and apparatus for defining vias
US7218491B2 (en) * 2002-12-23 2007-05-15 Intel Corporation Electrostatic discharge protection unit including equalization
US7823112B1 (en) 2003-05-30 2010-10-26 Golden Gate Technology, Inc. Method, software and system for ensuring timing between clocked components in a circuit
US7992122B1 (en) * 2005-03-25 2011-08-02 Gg Technology, Inc. Method of placing and routing for power optimization and timing closure
JP4850566B2 (ja) * 2006-04-12 2012-01-11 三菱電機株式会社 伝送特性解析装置及びプログラム
US7577933B1 (en) * 2006-11-17 2009-08-18 Sun Microsystems, Inc. Timing driven pin assignment
US8751999B2 (en) * 2011-07-05 2014-06-10 Fujitsu Limited Component placement tool for printed circuit board
US8935559B2 (en) * 2012-01-27 2015-01-13 Nvidia Corporation System and method for reducing crosstalk in on-chip networks using a contraflow interconnect and offset repeaters
JP6089849B2 (ja) * 2013-03-22 2017-03-08 富士通株式会社 プログラム、情報処理装置および設計検証方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306967A (en) * 1992-05-29 1994-04-26 Integrated Device Technology, Inc. Apparatus for improving signal transmission along parallel lines
US5481695A (en) * 1993-10-26 1996-01-02 Cadence Design Systems, Inc. System and method for estimating crosstalk between signal lines in a circuit
US5535133A (en) * 1995-02-09 1996-07-09 Unisys Corporation Method of fabricating IC chips with table look-up estimated crosstalk voltages being less than noise margin
US5687088A (en) * 1993-05-19 1997-11-11 Matsushita Electric Industrial Co., Ltd. Net list for use in logic simulation and back annotation method of feedbacking delay information obtained through layout design to logic simulation
US6185726B1 (en) * 1998-06-03 2001-02-06 Sony Corporation System and method for efficiently designing integrated circuit devices

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS607147A (ja) * 1983-06-24 1985-01-14 Mitsubishi Electric Corp 半導体装置
JP2753263B2 (ja) * 1988-05-13 1998-05-18 株式会社日立製作所 半導体集積回路の自動配線方法
US5123107A (en) * 1989-06-20 1992-06-16 Mensch Jr William D Topography of CMOS microcomputer integrated circuit chip including core processor and memory, priority, and I/O interface circuitry coupled thereto
US5287528A (en) * 1990-07-03 1994-02-15 National Instruments Corporation IEEE 488 interface for message handling method
JP3608832B2 (ja) * 1995-02-28 2005-01-12 富士通株式会社 自動配線方法および自動配線装置
GB9723440D0 (en) * 1997-11-06 1998-01-07 Int Computers Ltd Simulation model for a digital system
US6253359B1 (en) * 1998-01-29 2001-06-26 Texas Instruments Incorporated Method for analyzing circuit delays caused by capacitive coupling in digital circuits
US6175947B1 (en) * 1998-04-20 2001-01-16 International Business Machines Corporation Method of extracting 3-D capacitance and inductance parasitics in sub-micron VLSI chip designs using pattern recognition and parameterization
JP4560846B2 (ja) * 1998-07-23 2010-10-13 日本テキサス・インスツルメンツ株式会社 クロストーク防止回路
US6363516B1 (en) * 1999-11-12 2002-03-26 Texas Instruments Incorporated Method for hierarchical parasitic extraction of a CMOS design

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5306967A (en) * 1992-05-29 1994-04-26 Integrated Device Technology, Inc. Apparatus for improving signal transmission along parallel lines
US5687088A (en) * 1993-05-19 1997-11-11 Matsushita Electric Industrial Co., Ltd. Net list for use in logic simulation and back annotation method of feedbacking delay information obtained through layout design to logic simulation
US5481695A (en) * 1993-10-26 1996-01-02 Cadence Design Systems, Inc. System and method for estimating crosstalk between signal lines in a circuit
US5535133A (en) * 1995-02-09 1996-07-09 Unisys Corporation Method of fabricating IC chips with table look-up estimated crosstalk voltages being less than noise margin
US6185726B1 (en) * 1998-06-03 2001-02-06 Sony Corporation System and method for efficiently designing integrated circuit devices

Also Published As

Publication number Publication date
DE10205559A1 (de) 2002-08-29
JP2002318827A (ja) 2002-10-31
US20020112220A1 (en) 2002-08-15
US6567966B2 (en) 2003-05-20

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8125 Change of the main classification

Ipc: G06F 17/50

8127 New person/name/address of the applicant

Owner name: AVAGO TECHNOLOGIES GENERAL IP ( SINGAPORE) PTE. LT

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee