DE102013103082A1 - Niederspannungs-ESD-Begrenzung unter Verwendung von Hochspannungsbauelementen - Google Patents

Niederspannungs-ESD-Begrenzung unter Verwendung von Hochspannungsbauelementen Download PDF

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Publication number
DE102013103082A1
DE102013103082A1 DE102013103082A DE102013103082A DE102013103082A1 DE 102013103082 A1 DE102013103082 A1 DE 102013103082A1 DE 102013103082 A DE102013103082 A DE 102013103082A DE 102013103082 A DE102013103082 A DE 102013103082A DE 102013103082 A1 DE102013103082 A1 DE 102013103082A1
Authority
DE
Germany
Prior art keywords
region
esd protection
well
protection device
coupled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE102013103082A
Other languages
German (de)
English (en)
Inventor
Mayank Shrivastava
Christian Russ
Harald Gossner
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Deutschland GmbH
Original Assignee
Intel Mobile Communications GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US13/429,577 external-priority patent/US8681461B2/en
Priority claimed from US13/437,475 external-priority patent/US8654491B2/en
Application filed by Intel Mobile Communications GmbH filed Critical Intel Mobile Communications GmbH
Publication of DE102013103082A1 publication Critical patent/DE102013103082A1/de
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/0285—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements bias arrangements for gate electrode of field effect transistors, e.g. RC networks, voltage partitioning circuits
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE102013103082A 2012-03-26 2013-03-26 Niederspannungs-ESD-Begrenzung unter Verwendung von Hochspannungsbauelementen Pending DE102013103082A1 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US13/429,577 2012-03-26
US13/429,577 US8681461B2 (en) 2012-03-26 2012-03-26 Selective current pumping to enhance low-voltage ESD clamping using high voltage devices
US13/437,475 2012-04-02
US13/437,475 US8654491B2 (en) 2012-04-02 2012-04-02 Low voltage ESD clamping using high voltage devices

Publications (1)

Publication Number Publication Date
DE102013103082A1 true DE102013103082A1 (de) 2013-09-26

Family

ID=49112369

Family Applications (2)

Application Number Title Priority Date Filing Date
DE102013103082A Pending DE102013103082A1 (de) 2012-03-26 2013-03-26 Niederspannungs-ESD-Begrenzung unter Verwendung von Hochspannungsbauelementen
DE102013103076.9A Active DE102013103076B4 (de) 2012-03-26 2013-03-26 Selektives strompumpen zum verbessern der niederspannungs-esd-begrenzung unter verwendung von hochspannungsbauelementen

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE102013103076.9A Active DE102013103076B4 (de) 2012-03-26 2013-03-26 Selektives strompumpen zum verbessern der niederspannungs-esd-begrenzung unter verwendung von hochspannungsbauelementen

Country Status (2)

Country Link
CN (3) CN103367357B (zh)
DE (2) DE102013103082A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013103082A1 (de) * 2012-03-26 2013-09-26 Intel Mobile Communications GmbH Niederspannungs-ESD-Begrenzung unter Verwendung von Hochspannungsbauelementen
US9438034B2 (en) * 2014-01-15 2016-09-06 Nanya Technology Corporation Transient voltage suppressor
CN104835841B (zh) * 2015-05-08 2018-10-26 邓华鲜 Igbt芯片的结构
CN104966714B (zh) * 2015-05-08 2019-06-18 邓华鲜 Igbt芯片的控制方法
WO2016180258A1 (zh) * 2015-05-08 2016-11-17 邓华鲜 Igbt芯片的结构及其控制方法
JP6503395B2 (ja) * 2016-10-12 2019-04-17 イーメモリー テクノロジー インコーポレイテッド 静電放電回路
US11398468B2 (en) * 2019-12-12 2022-07-26 Micron Technology, Inc. Apparatus with voltage protection mechanism
CN114256822B (zh) * 2021-12-21 2024-05-07 电子科技大学 一种GaN基ESD保护电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411480B1 (en) * 1999-03-01 2002-06-25 International Business Machines Corporation Substrate pumped ESD network with trench structure
US6066879A (en) * 1999-05-03 2000-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Combined NMOS and SCR ESD protection device
US20030076636A1 (en) * 2001-10-23 2003-04-24 Ming-Dou Ker On-chip ESD protection circuit with a substrate-triggered SCR device
US6804095B2 (en) * 2002-06-05 2004-10-12 Texas Instruments Incorporated Drain-extended MOS ESD protection structure
JP3901671B2 (ja) 2003-08-19 2007-04-04 松下電器産業株式会社 半導体集積回路装置
US7245466B2 (en) * 2003-10-21 2007-07-17 Texas Instruments Incorporated Pumped SCR for ESD protection
US7872840B1 (en) * 2007-08-17 2011-01-18 National Semiconductor Corporation Erase pin protection in EEPROM using active snapback ESD device with positive feedback and shutdown
CN101488665A (zh) * 2008-01-18 2009-07-22 瑞鼎科技股份有限公司 静电放电保护电路
US7633731B1 (en) 2008-02-08 2009-12-15 Actel Corporation High-voltage dual-polarity I/O p-well pump ESD protection circuit
CN102136491B (zh) * 2008-11-03 2013-04-10 世界先进积体电路股份有限公司 栅极绝缘双接面晶体管静电放电防护元件
JP2010129893A (ja) * 2008-11-28 2010-06-10 Sony Corp 半導体集積回路
CN102237400B (zh) * 2010-04-30 2012-12-26 世界先进积体电路股份有限公司 静电放电防护装置
CN101916760A (zh) * 2010-05-28 2010-12-15 上海宏力半导体制造有限公司 一种有效避免闩锁效应的可控硅esd保护结构
DE102013103082A1 (de) * 2012-03-26 2013-09-26 Intel Mobile Communications GmbH Niederspannungs-ESD-Begrenzung unter Verwendung von Hochspannungsbauelementen

Also Published As

Publication number Publication date
CN103367357B (zh) 2016-02-24
CN103368158A (zh) 2013-10-23
CN107424988A (zh) 2017-12-01
CN107424988B (zh) 2021-02-02
CN103368158B (zh) 2016-12-28
DE102013103076B4 (de) 2022-03-17
CN103367357A (zh) 2013-10-23
DE102013103076A1 (de) 2013-09-26

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R012 Request for examination validly filed
R081 Change of applicant/patentee

Owner name: INTEL DEUTSCHLAND GMBH, DE

Free format text: FORMER OWNER: INTEL MOBILE COMMUNICATIONS GMBH, 85579 NEUBIBERG, DE

R082 Change of representative

Representative=s name: VIERING, JENTSCHURA & PARTNER MBB PATENT- UND , DE

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