DE102005051492B4 - Nichtflüchtiges Speicherbauelement mit Ladungseinfangstruktur und Herstellungsverfahren - Google Patents

Nichtflüchtiges Speicherbauelement mit Ladungseinfangstruktur und Herstellungsverfahren Download PDF

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Publication number
DE102005051492B4
DE102005051492B4 DE102005051492A DE102005051492A DE102005051492B4 DE 102005051492 B4 DE102005051492 B4 DE 102005051492B4 DE 102005051492 A DE102005051492 A DE 102005051492A DE 102005051492 A DE102005051492 A DE 102005051492A DE 102005051492 B4 DE102005051492 B4 DE 102005051492B4
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DE
Germany
Prior art keywords
charge trapping
gate electrode
layer
dielectric
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE102005051492A
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German (de)
English (en)
Other versions
DE102005051492A1 (de
Inventor
Sang-su Suwon Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1020050001267A external-priority patent/KR100714473B1/ko
Priority claimed from US11/167,051 external-priority patent/US7446371B2/en
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE102005051492A1 publication Critical patent/DE102005051492A1/de
Application granted granted Critical
Publication of DE102005051492B4 publication Critical patent/DE102005051492B4/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H10D30/6893—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode wherein the floating gate has multiple non-connected parts, e.g. multi-particle floating gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/696—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes having at least one additional gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/037—Manufacture or treatment of data-storage electrodes comprising charge-trapping insulators

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
DE102005051492A 2004-10-21 2005-10-19 Nichtflüchtiges Speicherbauelement mit Ladungseinfangstruktur und Herstellungsverfahren Expired - Lifetime DE102005051492B4 (de)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US62081104P 2004-10-21 2004-10-21
US60/620,811 2004-10-21
KR10-2005-0001267 2005-01-06
KR1020050001267A KR100714473B1 (ko) 2004-10-21 2005-01-06 비휘발성 메모리 소자 및 그 제조 방법
US11/167,051 US7446371B2 (en) 2004-10-21 2005-06-24 Non-volatile memory cell structure with charge trapping layers and method of fabricating the same
US11/167,051 2005-06-24

Publications (2)

Publication Number Publication Date
DE102005051492A1 DE102005051492A1 (de) 2006-04-27
DE102005051492B4 true DE102005051492B4 (de) 2008-02-28

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE102005051492A Expired - Lifetime DE102005051492B4 (de) 2004-10-21 2005-10-19 Nichtflüchtiges Speicherbauelement mit Ladungseinfangstruktur und Herstellungsverfahren

Country Status (2)

Country Link
JP (1) JP5143350B2 (https=)
DE (1) DE102005051492B4 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007158093A (ja) * 2005-12-06 2007-06-21 Sony Corp 不揮発性半導体メモリデバイス及びその製造方法
JP5205011B2 (ja) 2007-08-24 2013-06-05 ルネサスエレクトロニクス株式会社 不揮発性半導体装置およびその製造方法
JP4599421B2 (ja) * 2008-03-03 2010-12-15 株式会社東芝 半導体装置及びその製造方法
JP2011071334A (ja) * 2009-09-25 2011-04-07 Toshiba Corp 不揮発性半導体記憶装置
JP2013058810A (ja) * 2012-12-27 2013-03-28 Renesas Electronics Corp 不揮発性半導体装置およびその製造方法
JP6510289B2 (ja) 2015-03-30 2019-05-08 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030198086A1 (en) * 2002-04-18 2003-10-23 Shoji Shukuri Semiconductor integrated circuit device and a method of manufacturing the same
US20040021172A1 (en) * 2001-12-20 2004-02-05 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US6756271B1 (en) * 2002-03-12 2004-06-29 Halo Lsi, Inc. Simplified twin monos fabrication method with three extra masks to standard CMOS

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06318709A (ja) * 1993-03-12 1994-11-15 Citizen Watch Co Ltd 半導体不揮発性記憶装置およびその製造方法
JP4923321B2 (ja) * 2000-09-12 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置の動作方法
US6531350B2 (en) * 2001-02-22 2003-03-11 Halo, Inc. Twin MONOS cell fabrication method and array organization
JP2004303918A (ja) * 2003-03-31 2004-10-28 Renesas Technology Corp 半導体装置の製造方法および半導体装置
JP2005064178A (ja) * 2003-08-11 2005-03-10 Renesas Technology Corp 半導体装置およびその製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040021172A1 (en) * 2001-12-20 2004-02-05 Advanced Micro Devices, Inc. Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same
US6756271B1 (en) * 2002-03-12 2004-06-29 Halo Lsi, Inc. Simplified twin monos fabrication method with three extra masks to standard CMOS
US20030198086A1 (en) * 2002-04-18 2003-10-23 Shoji Shukuri Semiconductor integrated circuit device and a method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Lusky, E. [u.a.]: Characterization of Channel Hot Electron Injection by the Subthreshold Slope of NROM Device. In: IEEE Electron Device Letters, Bd. 22, Nr. 11, Nov. 2001, S. 556-558 *

Also Published As

Publication number Publication date
JP2006121094A (ja) 2006-05-11
JP5143350B2 (ja) 2013-02-13
DE102005051492A1 (de) 2006-04-27

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Ipc: H10B0069000000

R071 Expiry of right