DE10133873B4 - Verfahren zur Herstellung von Kontakten für integrierte Schaltungen - Google Patents
Verfahren zur Herstellung von Kontakten für integrierte Schaltungen Download PDFInfo
- Publication number
- DE10133873B4 DE10133873B4 DE10133873A DE10133873A DE10133873B4 DE 10133873 B4 DE10133873 B4 DE 10133873B4 DE 10133873 A DE10133873 A DE 10133873A DE 10133873 A DE10133873 A DE 10133873A DE 10133873 B4 DE10133873 B4 DE 10133873B4
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuits
- making contacts
- contacts
- making
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10133873A DE10133873B4 (de) | 2001-07-12 | 2001-07-12 | Verfahren zur Herstellung von Kontakten für integrierte Schaltungen |
PCT/EP2002/007507 WO2003007355A2 (de) | 2001-07-12 | 2002-07-05 | Verfahren zur herstellung von kontakten für integrierte schaltungen und halbleiterbauelement mit solchen kontakten |
TW091115073A TW557502B (en) | 2001-07-12 | 2002-07-08 | Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts |
KR1020047000251A KR100592581B1 (ko) | 2001-07-12 | 2004-01-08 | 집적 회로용 콘택의 제조 방법 및 상기 콘택을 가진반도체 소자 |
US10/754,439 US7265405B2 (en) | 2001-07-12 | 2004-01-09 | Method for fabricating contacts for integrated circuits, and semiconductor component having such contacts |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10133873A DE10133873B4 (de) | 2001-07-12 | 2001-07-12 | Verfahren zur Herstellung von Kontakten für integrierte Schaltungen |
Publications (2)
Publication Number | Publication Date |
---|---|
DE10133873A1 DE10133873A1 (de) | 2003-01-30 |
DE10133873B4 true DE10133873B4 (de) | 2005-04-28 |
Family
ID=7691515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10133873A Expired - Fee Related DE10133873B4 (de) | 2001-07-12 | 2001-07-12 | Verfahren zur Herstellung von Kontakten für integrierte Schaltungen |
Country Status (5)
Country | Link |
---|---|
US (1) | US7265405B2 (de) |
KR (1) | KR100592581B1 (de) |
DE (1) | DE10133873B4 (de) |
TW (1) | TW557502B (de) |
WO (1) | WO2003007355A2 (de) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102005053509A1 (de) * | 2005-09-30 | 2007-04-05 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterprodukts und Halbleiterprodukt |
DE10219841B4 (de) * | 2001-05-18 | 2007-11-29 | Infineon Technologies North America Corp., San Jose | Kontaktplugausbildung für Bauelemente mit gestapelten Kondensatoren |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW200425298A (en) * | 2003-05-01 | 2004-11-16 | Nanya Technology Corp | Fabrication method for a damascene bitline contact |
US7241705B2 (en) * | 2004-09-01 | 2007-07-10 | Micron Technology, Inc. | Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects |
US7416976B2 (en) * | 2005-08-31 | 2008-08-26 | Infineon Technologies Ag | Method of forming contacts using auxiliary structures |
US9378968B2 (en) * | 2014-09-02 | 2016-06-28 | United Microelectronics Corporation | Method for planarizing semiconductor device |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4662064A (en) * | 1985-08-05 | 1987-05-05 | Rca Corporation | Method of forming multi-level metallization |
EP0365493A2 (de) * | 1988-10-20 | 1990-04-25 | STMicroelectronics S.r.l. | Herstellen von selbstjustierenden Kontakten ohne Maske |
WO1999044232A1 (en) * | 1998-02-27 | 1999-09-02 | Micron Technology, Inc. | Method of increasing alignment tolerances for interconnect structures |
US5981326A (en) * | 1998-03-23 | 1999-11-09 | Wanlass; Frank M. | Damascene isolation of CMOS transistors |
JP2001035808A (ja) * | 1999-07-22 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5362666A (en) * | 1992-09-18 | 1994-11-08 | Micron Technology, Inc. | Method of producing a self-aligned contact penetrating cell plate |
US6027997A (en) * | 1994-03-04 | 2000-02-22 | Motorola, Inc. | Method for chemical mechanical polishing a semiconductor device using slurry |
US5541870A (en) * | 1994-10-28 | 1996-07-30 | Symetrix Corporation | Ferroelectric memory and non-volatile memory cell for same |
JP2814972B2 (ja) * | 1995-12-18 | 1998-10-27 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2971411B2 (ja) * | 1997-01-28 | 1999-11-08 | 台湾茂▲しい▼電子股▲ふん▼有限公司 | Dramのビット線セルフアライン工程及び基板を破壊しないイオンレイアウト工程 |
US6329681B1 (en) * | 1997-12-18 | 2001-12-11 | Yoshitaka Nakamura | Semiconductor integrated circuit device and method of manufacturing the same |
US6096633A (en) * | 1998-10-28 | 2000-08-01 | United Microelectronics Corp. | Dual damascene process for forming local interconnect |
US6180453B1 (en) * | 1998-12-21 | 2001-01-30 | Vanguard International Semiconductor Corporation | Method to fabricate a DRAM cell with an area equal to five times the minimum used feature, squared |
TW415089B (en) * | 1999-05-07 | 2000-12-11 | Taiwan Semiconductor Mfg | Fabrication method of landing pad |
TW408446B (en) * | 1999-06-22 | 2000-10-11 | United Microelectronics Corp | The manufacture method of the node contact |
KR100322536B1 (ko) * | 1999-06-29 | 2002-03-18 | 윤종용 | 에치 백을 이용한 다결정 실리콘 컨택 플러그 형성방법 및 이를 이용한 반도체 소자의 제조방법 |
DE19935852A1 (de) | 1999-07-29 | 2001-02-01 | Infineon Technologies Ag | Verfahren zur Herstellung integrierter Halbleiterbauelemente |
US6159808A (en) * | 1999-11-12 | 2000-12-12 | United Semiconductor Corp. | Method of forming self-aligned DRAM cell |
DE10119873A1 (de) | 2001-04-24 | 2002-10-31 | Infineon Technologies Ag | Verfahren zur Herstellung von Metall/Halbleiter-Kontakten |
-
2001
- 2001-07-12 DE DE10133873A patent/DE10133873B4/de not_active Expired - Fee Related
-
2002
- 2002-07-05 WO PCT/EP2002/007507 patent/WO2003007355A2/de active Application Filing
- 2002-07-08 TW TW091115073A patent/TW557502B/zh not_active IP Right Cessation
-
2004
- 2004-01-08 KR KR1020047000251A patent/KR100592581B1/ko not_active IP Right Cessation
- 2004-01-09 US US10/754,439 patent/US7265405B2/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4662064A (en) * | 1985-08-05 | 1987-05-05 | Rca Corporation | Method of forming multi-level metallization |
EP0365493A2 (de) * | 1988-10-20 | 1990-04-25 | STMicroelectronics S.r.l. | Herstellen von selbstjustierenden Kontakten ohne Maske |
WO1999044232A1 (en) * | 1998-02-27 | 1999-09-02 | Micron Technology, Inc. | Method of increasing alignment tolerances for interconnect structures |
US5981326A (en) * | 1998-03-23 | 1999-11-09 | Wanlass; Frank M. | Damascene isolation of CMOS transistors |
JP2001035808A (ja) * | 1999-07-22 | 2001-02-09 | Semiconductor Energy Lab Co Ltd | 配線およびその作製方法、この配線を備えた半導体装置、ドライエッチング方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10219841B4 (de) * | 2001-05-18 | 2007-11-29 | Infineon Technologies North America Corp., San Jose | Kontaktplugausbildung für Bauelemente mit gestapelten Kondensatoren |
DE102005053509A1 (de) * | 2005-09-30 | 2007-04-05 | Infineon Technologies Ag | Verfahren zur Herstellung eines Halbleiterprodukts und Halbleiterprodukt |
Also Published As
Publication number | Publication date |
---|---|
WO2003007355A3 (de) | 2003-09-18 |
KR20040015792A (ko) | 2004-02-19 |
KR100592581B1 (ko) | 2006-06-26 |
US20040195596A1 (en) | 2004-10-07 |
DE10133873A1 (de) | 2003-01-30 |
US7265405B2 (en) | 2007-09-04 |
TW557502B (en) | 2003-10-11 |
WO2003007355A2 (de) | 2003-01-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
OP8 | Request for examination as to paragraph 44 patent law | ||
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: QIMONDA AG, 81739 MUENCHEN, DE |
|
R081 | Change of applicant/patentee |
Owner name: INFINEON TECHNOLOGIES AG, DE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: QIMONDA AG, 81739 MUENCHEN, DE |
|
R081 | Change of applicant/patentee |
Owner name: POLARIS INNOVATIONS LTD., IE Free format text: FORMER OWNER: INFINEON TECHNOLOGIES AG, 85579 NEUBIBERG, DE |
|
R119 | Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee |