DE10085097B4 - Verfahren und Einrichtung zum Steuern kompensierter Puffer - Google Patents

Verfahren und Einrichtung zum Steuern kompensierter Puffer Download PDF

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Publication number
DE10085097B4
DE10085097B4 DE10085097T DE10085097T DE10085097B4 DE 10085097 B4 DE10085097 B4 DE 10085097B4 DE 10085097 T DE10085097 T DE 10085097T DE 10085097 T DE10085097 T DE 10085097T DE 10085097 B4 DE10085097 B4 DE 10085097B4
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DE
Germany
Prior art keywords
compensation value
integrated circuit
compensation
value
digital
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10085097T
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German (de)
English (en)
Other versions
DE10085097T1 (de
Inventor
Brian Chandler Possley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE10085097T1 publication Critical patent/DE10085097T1/de
Application granted granted Critical
Publication of DE10085097B4 publication Critical patent/DE10085097B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Non-Silver Salt Photosensitive Materials And Non-Silver Salt Photography (AREA)
  • Record Information Processing For Printing (AREA)
  • Developing Agents For Electrophotography (AREA)
DE10085097T 1999-10-15 2000-09-27 Verfahren und Einrichtung zum Steuern kompensierter Puffer Expired - Fee Related DE10085097B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/418,762 US6300798B1 (en) 1999-10-15 1999-10-15 Method and apparatus for controlling compensated buffers
US09/418,762 1999-10-15
PCT/US2000/026547 WO2001029967A1 (en) 1999-10-15 2000-09-27 Method and apparatus for controlling compensated buffers

Publications (2)

Publication Number Publication Date
DE10085097T1 DE10085097T1 (de) 2002-09-19
DE10085097B4 true DE10085097B4 (de) 2008-12-18

Family

ID=23659472

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10085097T Expired - Fee Related DE10085097B4 (de) 1999-10-15 2000-09-27 Verfahren und Einrichtung zum Steuern kompensierter Puffer

Country Status (8)

Country Link
US (1) US6300798B1 (enExample)
JP (1) JP2003512753A (enExample)
KR (1) KR100563106B1 (enExample)
AU (1) AU7722200A (enExample)
DE (1) DE10085097B4 (enExample)
GB (1) GB2371694B (enExample)
TW (1) TW517454B (enExample)
WO (1) WO2001029967A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6545522B2 (en) * 2001-05-17 2003-04-08 Intel Corporation Apparatus and method to provide a single reference component for multiple circuit compensation using digital impedance code shifting
US6535047B2 (en) * 2001-05-17 2003-03-18 Intel Corporation Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation
US6633178B2 (en) * 2001-09-28 2003-10-14 Intel Corporation Apparatus and method for power efficient line driver
JP4502177B2 (ja) * 2003-10-14 2010-07-14 ルネサスエレクトロニクス株式会社 出力回路
US7009894B2 (en) * 2004-02-19 2006-03-07 Intel Corporation Dynamically activated memory controller data termination

Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079456A (en) * 1977-01-24 1978-03-14 Rca Corporation Output buffer synchronizing circuit having selectively variable delay means
JPS63135882A (ja) * 1986-11-28 1988-06-08 Hitachi Electronics Eng Co Ltd 電子デバイス駆動回路
EP0606727A1 (en) * 1993-01-13 1994-07-20 AT&T Corp. Automatic control of buffer speed
EP0611053A2 (en) * 1993-02-08 1994-08-17 Advanced Micro Devices, Inc. Buffer circuits
JPH0722597A (ja) * 1993-06-23 1995-01-24 Kawasaki Steel Corp 半導体集積回路装置
US5463331A (en) * 1993-06-08 1995-10-31 National Semiconductor Corporation Programmable slew rate CMOS buffer and transmission line driver with temperature compensation
EP0714167A1 (de) * 1994-11-22 1996-05-29 Deutsche ITT Industries GmbH Digitale Treiberschaltung für eine integrierte Schaltung
EP0718977A2 (en) * 1994-12-20 1996-06-26 STMicroelectronics, Inc. Output driver circuitry with selectable limited output high voltage
US5717313A (en) * 1994-09-13 1998-02-10 Norand Corporation Battery charging method and apparatus with thermal mass equalization
JPH1117516A (ja) * 1997-06-10 1999-01-22 Ind Technol Res Inst 制御されたスルーレートを有する高速及び低速出力バッファー
US5870001A (en) * 1996-10-22 1999-02-09 Telefonaktiebolaget L M Ericsson (Publ) Apparatus, and associated method, for calibrating a device
US5869983A (en) * 1997-03-24 1999-02-09 Intel Corporation Method and apparatus for controlling compensated buffers
US5883801A (en) * 1996-05-14 1999-03-16 Microwave Science, Llc Method and apparatus for managing electromagnetic radiation usage
US5898321A (en) * 1997-03-24 1999-04-27 Intel Corporation Method and apparatus for slew rate and impedance compensating buffer circuits

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4975598A (en) * 1988-12-21 1990-12-04 Intel Corporation Temperature, voltage, and process compensated output driver
JPH0583111A (ja) * 1991-09-24 1993-04-02 Nec Ic Microcomput Syst Ltd Ｃｍｏｓ集積回路
US5303191A (en) * 1992-01-23 1994-04-12 Motorola, Inc. Memory with compensation for voltage, temperature, and processing variations
US5640122A (en) * 1994-12-16 1997-06-17 Sgs-Thomson Microelectronics, Inc. Circuit for providing a bias voltage compensated for p-channel transistor variations
US5959481A (en) * 1997-02-18 1999-09-28 Rambus Inc. Bus driver circuit including a slew rate indicator circuit having a one shot circuit
US6031385A (en) 1997-03-24 2000-02-29 Intel Corporation Method and apparatus for testing compensated buffer circuits
US6092030A (en) * 1997-04-02 2000-07-18 Credence Systems Corporation Timing delay generator and method including compensation for environmental variation
US5912569A (en) * 1997-09-22 1999-06-15 Cypress Semiconductor Corp. Methods, circuits and devices for improving crossover performance and/or monotonicity, and applications of the same in a universal serial bus (USB) low speed output driver

Patent Citations (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079456A (en) * 1977-01-24 1978-03-14 Rca Corporation Output buffer synchronizing circuit having selectively variable delay means
JPS63135882A (ja) * 1986-11-28 1988-06-08 Hitachi Electronics Eng Co Ltd 電子デバイス駆動回路
EP0606727A1 (en) * 1993-01-13 1994-07-20 AT&T Corp. Automatic control of buffer speed
EP0611053A2 (en) * 1993-02-08 1994-08-17 Advanced Micro Devices, Inc. Buffer circuits
US5463331A (en) * 1993-06-08 1995-10-31 National Semiconductor Corporation Programmable slew rate CMOS buffer and transmission line driver with temperature compensation
JPH0722597A (ja) * 1993-06-23 1995-01-24 Kawasaki Steel Corp 半導体集積回路装置
US5717313A (en) * 1994-09-13 1998-02-10 Norand Corporation Battery charging method and apparatus with thermal mass equalization
EP0714167A1 (de) * 1994-11-22 1996-05-29 Deutsche ITT Industries GmbH Digitale Treiberschaltung für eine integrierte Schaltung
EP0718977A2 (en) * 1994-12-20 1996-06-26 STMicroelectronics, Inc. Output driver circuitry with selectable limited output high voltage
US5883801A (en) * 1996-05-14 1999-03-16 Microwave Science, Llc Method and apparatus for managing electromagnetic radiation usage
US5870001A (en) * 1996-10-22 1999-02-09 Telefonaktiebolaget L M Ericsson (Publ) Apparatus, and associated method, for calibrating a device
US5869983A (en) * 1997-03-24 1999-02-09 Intel Corporation Method and apparatus for controlling compensated buffers
US5898321A (en) * 1997-03-24 1999-04-27 Intel Corporation Method and apparatus for slew rate and impedance compensating buffer circuits
JPH1117516A (ja) * 1997-06-10 1999-01-22 Ind Technol Res Inst 制御されたスルーレートを有する高速及び低速出力バッファー

Also Published As

Publication number Publication date
KR20020060712A (ko) 2002-07-18
WO2001029967A1 (en) 2001-04-26
KR100563106B1 (ko) 2006-03-27
HK1044639A1 (en) 2002-10-25
US6300798B1 (en) 2001-10-09
GB0210910D0 (en) 2002-06-19
DE10085097T1 (de) 2002-09-19
GB2371694A (en) 2002-07-31
GB2371694B (en) 2004-07-21
TW517454B (en) 2003-01-11
AU7722200A (en) 2001-04-30
JP2003512753A (ja) 2003-04-02

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Legal Events

Date Code Title Description
8110 Request for examination paragraph 44
8364 No opposition during term of opposition
R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20140401