Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03K—PULSE TECHNIQUE
  • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
  • H03K19/003—Modifications for increasing the reliability for protection
  • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
  • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits

Definitions

• the physical arrangement of transistors within a die as compared to the arrangement of other transistors may result in some of the transistors undergoing greater electro-mechanical stress during operation. This problem may be further acerbated by the operating conditions, such as temperature, for example, which may be imposed upon the device by a consumer. If the variation in performance becomes too extreme, the device may operate outside the range deemed acceptable by a customer. If this
• FIG. 1 is a block diagram representation of a portion of an integrated circuit having a compensation unit and a compensation value generator in accordance with an embodiment of the present invention
• FIG. 2 is a schematic diagram representation of the embodiment of the compensation unit shown in FIG. 1 ;
• FIG. 3 is a graph illustrating the effect the embodiment of FIG. 1 may have upon the performance of some transistors in the integrated circuit.
• FIG. 1 is a block diagram representation of a portion of an integrated circuit 10 in accordance with an embodiment of the invention. Embodiments of
• integrated circuit 10 may comprise a variety of semiconductor devices including, for example, a microprocessor, a microcontroller, a static random access memory (SRAM), a dynamic random access memory (DRAM), a non-volatile memory, or the like.
• SRAM static random access memory
• DRAM dynamic random access memory
• integrated circuit 10 may include a compensation value generator 15.
• a compensation value generator comprises any device that receives as input signals two or more values and performs operations upon those received values to produce a value as an output signal that may perform mathematical algorithms (i.e., processes) with a variety of compensation values to provide integrated circuit 10 with an updated compensation value that may be used to adjust the performance of all or part of integrated circuit 10.
• compensation value generator 15 may include logic transistors or switches that process the compensation value provided by two different sources to calculate an updated compensation value.
• the compensation values processed by compensation value generator 15 may comprise digital values provided by sources external to compensation value generator 15 such as other circuitry, memory locations, a user interface, or the like.
• the updated compensation value may then used by other portions of integrated circuit 10 (e.g., compensation buffers) to adjust the performance of other transistors (not shown) within integrated circuit 10 by
• I/O input/output
• compensated buffer for example.
• compensation value generator 15 processes compensation values 18 and 19 to be provided by memory locations 16 and 17, respectively.
• compensation value generator 15 may be modified so as to process a plurality of compensation values and that the present invention is not limited to adding just two values.
• neither of compensation values 18 and 19 need to be stored in a memory location as they may be provided dynamically as
• Compensation value 18 represents a binary compensation value that is determined by other circuitry within or external to integrated circuit 10.
• An example of such circuitry is shown in FIG. 2.
• Fig. 2 illustrates circuitry that may be used to determine compensation value 18.
• the circuitry includes a compensation unit 30 that is connected to a comparator 35 and transistors 31-33. It should be understood that the present invention is not limited to this particular configuration as another comparator device could be employed and the number of transistors connected to compensation unit 30 can be altered.
• compensation unit 30 performs an analysis on a sub-set of the transistors within integrated circuit 10. This analysis results in generating a compensation value that is used by other portions of integrated
• the compensation value is a sequence of binary values that indicates the result of the analysis by the compensation unit.
• comparator 35 compares a reference voltage (V REF ) at node 36 against the voltage provided at node 37.
• the voltage at node 37 is determined at least in part by the voltage provided at node 38 (e.g., power supply voltage, V C c) and the voltage drop due to current flowing through resistor element 40.
• Logic circuitry within compensation unit 30 is used to enable/disable each of transistors 31-33 until the current flow through transistors 31-33 is sufficient so that the voltage at node 37 is approximately equal to the voltage at node 36.
• each of transistors 31-33 i.e., enabled or disabled
• compensation unit 30 represents all or part of compensation value 18 (see FIG. 1).
• Compensation value 18 may then be stored in a memory location 16 (e.g., cache, register, etc.) or be dynamically provided to adder 15 as desired.
• compensation value generator 15 also processes a compensation value 19 stored in memory location 17. Again, this is not a requirement of this embodiment of the present invention as compensation value 19 may be dynamically provided to compensation value generator 15, for example.
• Compensation value 19 comprises an adjustable value that may be varied, for example, through software such as the basic input/output system (BIOS) that is used to control the operation of integrated circuits (BIOS).
• BIOS basic input/output system
• the integrated circuit may begin an initialization routine.
• the instructions for the initialization routine may be stored as BIOS instructions.
• BIOS instructions may be used for a variety of reasons and may be used to pre-set values within the integrated circuit.
• the BIOS instructions may be used to initialize values stored in
• the BIOS instructions may be used to load memory location 17 with a compensation value. Therefore, the value loaded into memory location 17 may be pre-determined by the manufacturer of integrated circuit 10 so that an initial value is stored each time integrated circuit 10 is turned on. Furthermore, the initial value may be adjusted by a consumer who has the ability to modify the BIOS instructions.
• compensation value 19 comprises an adjustable or programmable compensation value that is used to fine-tune the performance of integrated circuit 10.
• the magnitude or value of compensation value 19 may be determined at least in part by the actual value of compensation value 18, a predicted value for compensation value 18, or a value that represents the least amount of compensation desired for integrated circuit 10.
• compensation value 19 may be determined at least in part by the actual value of compensation value 18, a predicted value for compensation value 18, or a value that represents the least amount of compensation desired for integrated circuit 10.
• compensation value 19 may be determined at least in part by the actual value of compensation value 18, a predicted value for compensation value 18, or a value that represents the least amount of compensation desired for integrated circuit 10.
• compensation value 19 may be used to add to, reduce, or adjust the compensation value provided by compensation unit 30. This provides for the fine tuning of the compensation that is applied to the transistors in integrated circuit 10.
• compensation value 19 may be a binary string determined by an integrated circuit manufacturer to improve the operation of integrated circuit 10 for applications having particular temperature, voltage, frequency, etc., ranges. A manufacturer may also adjust compensation value 19 to
• tuning may be beneficial depending on a variety of factors such as the package used to encase integrated circuit 10 or the application of a particular customer, for example.
• FIG. 3 is provided to illustrate one example of how an embodiment of the present invention may be used to adjust the performance of an integrated circuit.
• integrated circuit 10 includes both p-channel metal- oxide semiconductor (PMOS) and n-channel metal-oxide semiconductor (NMOS) transistors, although the invention is not limited in scope in this respect.
• FIG. 3 is a graph of the current/voltage (l/V) characteristics of one PMOS device (line 50) against an NMOS device (line 51 ). As shown, the NMOS device is not as linear as the PMOS device. Consequently, the sourcing vs. sinking capability of transistors within integrated circuit 50 may not be ideal. Consequently, it may be desirable to adjust the slope of NMOS devices to improve the operation of integrated circuit 10.
• a compensation unit such as the one shown in FIG. 2, may be used to adjust the performance of the NMOS devices.
• a compensation unit may determine the amount of compensation desired and this compensation is then may be implemented with compensation circuitry (not shown).
• a compensation circuit may be used adjust the linearity of the NMOS devices as shown in FIG. 3 with lines 60 and 61 (the uncompensated performance indicated with line 60 and the compensated performance indicated with line 61 ).
• the magnitude of the effect of the compensation is indicated in FIG. 3 with a bracket 62.
• the compensation that is utilized to adjust the performance is represented as a binary, compensation value.
• an embodiment of the present invention may employ a comparison circuit that compares the operation of a PMOS transistor against the operation of an NMOS transistor to generate a compensation value. This adjusted or programmable compensation value is then added to the compensation value by compensation value generator 15 (see FIG. 1 ) to provide integrated circuit 10 with an updated compensation value.
• compensation value generator 15 performs binary, bit-by-bit addition of compensation value 18 and compensation value 19 to provide an updated calculated compensation value 25.
• compensation value generator 15 may be desirable for compensation value generator 15 to perform other processing such as only partial addition, multiplication, or to simply determine which of a set of values is larger. Consequently, compensation value generator 15
• calculated compensation value 25 may be used by compensation circuitry, such as a compensated buffer 28, to adjust the operational performance of integrated circuit 10.
• compensated buffer 28 may decode calculated compensation value 25 and activate the appropriate circuitry to provide integrated circuit 10 with the desired compensation.
• calculated compensation value 25 may be optionally stored in a memory location 26.
• selection circuitry (not shown) may be added to the circuit shown in FIG. 1 so that compensated buffer 28 receives compensation value 18, compensation value 19, or calculated compensation value 25.
• an external read/write signal line may be added to allow an externally generated value to be written into memory location 26.
• integrated circuit 10 may include a clamp 27 that is connected to the calculated compensation value 25 provided by compensation value generator 15 as shown in FIG. 1.
• clamp 27 may be omitted and the invention is not restricted in scope to require inclusion of a clamp.
• clamp 27 is designed to have an acceptable clamp range and is used to determine if the value generated by compensation value generator 15 is outside this acceptable range. If calculated compensation value 25 is not within the acceptable range, then clamp 27 may intervene to provide compensated buffer 28 with an alternative compensation value. This feature may be desirable, for example, if compensation value 18 and/or compensation value 19 comprise a negative value, or if the processing performed by compensation value generator 15 results in a value that is an undesirable adjustment in the performance of integrated circuit 10.
• clamp 27 may be used to ensure a selected minimal amount of compensation or to prevent excessive compensation within integrated circuit 10.
• compensation value 19 may be provided by a series of fuses 20 or stored in a non-volatile memory (e.g., electrically erasable and programmable read-only memory (EEPROM), electrically programmable read-only memory (EPROM), Flash EEPROM, etc.) located within or external to integrated circuit 10.
• EEPROM electrically erasable and programmable read-only memory
• EPROM electrically programmable read-only memory
• Flash EEPROM etc.
• compensation value 19 may be provided to integrated circuit 10 through a user interface.
• a user interface may be, for example, a bus or register that allows a user to provide compensation value 19 from an external source. This may give either the manufacturer of an integrated circuit or a consumer the flexibility to adjust the amount of compensation applied within integrated circuit 10, for example.
• this embodiment of the present invention provides a circuit for compensating the performance of an integrated circuit.
• This embodiment offers advantages not available with prior techniques, such as described in aforementioned US Patent 5,869,983 because this embodiment allows the compensation value provided by two or more sources to be combined as desired to provide for improved tuning of the performance of integrated circuits.
• Prior techniques only allowed for selecting one of two compensation values and did not provide for the processing of the two values to provide a third value that was based at least in part on the two input values.
• FIGs. 1-2 provides flexibility not previously available.
• adder 15 could be modified so as to allow for the processing of multiple input values. It is, therefore, to be understood that the appended claims are intended to cover

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Citations (14)

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• 1999
  • 1999-10-15 US US09/418,762 patent/US6300798B1/en not_active Expired - Fee Related
• 2000
  • 2000-09-27 GB GB0210910A patent/GB2371694B/en not_active Expired - Fee Related
  • 2000-09-27 DE DE10085097T patent/DE10085097B4/de not_active Expired - Fee Related
  • 2000-09-27 AU AU77222/00A patent/AU7722200A/en not_active Abandoned
  • 2000-09-27 WO PCT/US2000/026547 patent/WO2001029967A1/en not_active Ceased
  • 2000-09-27 KR KR1020027004795A patent/KR100563106B1/ko not_active Expired - Fee Related
  • 2000-09-27 JP JP2001531206A patent/JP2003512753A/ja active Pending
  • 2000-10-27 TW TW089121449A patent/TW517454B/zh not_active IP Right Cessation

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