DE10012079B4 - Taktsteuerschaltung und -Verfahren - Google Patents

Taktsteuerschaltung und -Verfahren Download PDF

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Publication number
DE10012079B4
DE10012079B4 DE10012079A DE10012079A DE10012079B4 DE 10012079 B4 DE10012079 B4 DE 10012079B4 DE 10012079 A DE10012079 A DE 10012079A DE 10012079 A DE10012079 A DE 10012079A DE 10012079 B4 DE10012079 B4 DE 10012079B4
Authority
DE
Germany
Prior art keywords
clock
output
frequency
multiplication factor
pll
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE10012079A
Other languages
German (de)
English (en)
Other versions
DE10012079A1 (de
Inventor
Atsushi Kawasaki Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE10012079A1 publication Critical patent/DE10012079A1/de
Application granted granted Critical
Publication of DE10012079B4 publication Critical patent/DE10012079B4/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Power Sources (AREA)
DE10012079A 1999-08-12 2000-03-14 Taktsteuerschaltung und -Verfahren Expired - Fee Related DE10012079B4 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11228678A JP2001051747A (ja) 1999-08-12 1999-08-12 クロック制御回路
JPP11-228678 1999-08-12
US09/538,523 US6529083B2 (en) 1999-08-12 2000-03-30 Clock control circuit

Publications (2)

Publication Number Publication Date
DE10012079A1 DE10012079A1 (de) 2001-03-01
DE10012079B4 true DE10012079B4 (de) 2005-02-17

Family

ID=26528400

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10012079A Expired - Fee Related DE10012079B4 (de) 1999-08-12 2000-03-14 Taktsteuerschaltung und -Verfahren

Country Status (3)

Country Link
US (1) US6529083B2 (enExample)
JP (1) JP2001051747A (enExample)
DE (1) DE10012079B4 (enExample)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6871051B1 (en) * 2000-06-26 2005-03-22 Keith Barr Serial data transmission system using minimal interface
JP2002041452A (ja) * 2000-07-27 2002-02-08 Hitachi Ltd マイクロプロセッサ、半導体モジュール及びデータ処理システム
JP3587162B2 (ja) * 2000-10-31 2004-11-10 セイコーエプソン株式会社 データ転送制御装置及び電子機器
GB0123421D0 (en) * 2001-09-28 2001-11-21 Memquest Ltd Power management system
US7036032B2 (en) * 2002-01-04 2006-04-25 Ati Technologies, Inc. System for reduced power consumption by phase locked loop and method thereof
JP3665030B2 (ja) 2002-02-19 2005-06-29 Ｎｅｃマイクロシステム株式会社 バス制御方法及び情報処理装置
US7210054B2 (en) * 2002-06-25 2007-04-24 Intel Corporation Maintaining processor execution during frequency transitioning
US7278047B2 (en) * 2002-10-14 2007-10-02 Lexmark International, Inc. Providing different clock frequencies for different interfaces of a device
US7100065B2 (en) * 2003-05-09 2006-08-29 Hewlett-Packard Development Company, L.P. Controller arrangement for synchronizer data transfer between a core clock domain and bus clock domain each having its own individual synchronizing controller
US7219251B2 (en) * 2003-05-09 2007-05-15 Hewlett-Packard Development Company, L.P. Programmable clock synchronizer
US7194650B2 (en) * 2003-05-09 2007-03-20 Hewlett-Packard Development Company, L.P. System and method for synchronizing multiple synchronizer controllers
US7245684B2 (en) * 2003-05-09 2007-07-17 Hewlett-Packard Development Company, L.P. System and method for compensating for skew between a first clock signal and a second clock signal
US7315957B1 (en) * 2003-12-18 2008-01-01 Nvidia Corporation Method of providing a second clock while changing a first supplied clock frequency then supplying the changed first clock
US7340631B2 (en) * 2004-07-23 2008-03-04 Hewlett-Packard Development Company, L.P. Drift-tolerant sync pulse circuit in a sync pulse generator
US7119582B2 (en) * 2004-07-23 2006-10-10 Hewlett-Packard Development Company, Lp. Phase detection in a sync pulse generator
US7382847B2 (en) * 2004-07-23 2008-06-03 Hewlett-Packard Development Company, L.P. Programmable sync pulse generator
US7436917B2 (en) * 2004-07-29 2008-10-14 Hewlett-Packard Development Company, L.P. Controller for clock synchronizer
US20060023819A1 (en) * 2004-07-29 2006-02-02 Adkisson Richard W Clock synchronizer
KR100714396B1 (ko) * 2005-07-18 2007-05-04 삼성전자주식회사 메모리의 처리속도를 향상시킨 컴퓨터 시스템
JP4402021B2 (ja) * 2005-08-08 2010-01-20 パナソニック株式会社 半導体集積回路
US9262837B2 (en) 2005-10-17 2016-02-16 Nvidia Corporation PCIE clock rate stepping for graphics and platform processors
JP2007133527A (ja) * 2005-11-09 2007-05-31 Fujifilm Corp クロック信号生成回路、半導体集積回路及び分周率制御方法
US7664213B2 (en) * 2005-11-22 2010-02-16 Sun Microsystems, Inc. Clock alignment detection from single reference
WO2011067625A1 (en) * 2009-12-01 2011-06-09 Nxp B.V. A system for processing audio data
JP5172872B2 (ja) * 2010-01-28 2013-03-27 日本電信電話株式会社 クロック・データリカバリ回路
WO2014093878A1 (en) * 2012-12-13 2014-06-19 Coherent Logix, Incorporated Automatic selection of on-chip clock in synchronous digital systems
JP5885695B2 (ja) * 2013-03-26 2016-03-15 京セラドキュメントソリューションズ株式会社 集積回路およびクロック設定変更方法
CN104184470B (zh) * 2014-09-01 2017-04-19 福州瑞芯微电子股份有限公司 Pll修改自动复位装置及方法
JP6374350B2 (ja) * 2015-05-25 2018-08-15 大崎電気工業株式会社 タイマ同期システム

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972442A (en) * 1989-04-27 1990-11-20 Northern Telecom Limited Phase-locked loop clock
US5142247A (en) * 1991-08-06 1992-08-25 Compaq Computer Corporation Multiple frequency phase-locked loop clock generator with stable transitions between frequencies
US5161175A (en) * 1991-05-28 1992-11-03 Motorola, Inc. Circuit and method of detecting an invalid clock signal
JPH0854955A (ja) * 1994-08-10 1996-02-27 Fujitsu Ltd クロック信号発生回路

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903748A (en) * 1997-08-18 1999-05-11 Motorola Inc. Method and apparatus for managing failure of a system clock in a data processing system

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4972442A (en) * 1989-04-27 1990-11-20 Northern Telecom Limited Phase-locked loop clock
US5161175A (en) * 1991-05-28 1992-11-03 Motorola, Inc. Circuit and method of detecting an invalid clock signal
US5142247A (en) * 1991-08-06 1992-08-25 Compaq Computer Corporation Multiple frequency phase-locked loop clock generator with stable transitions between frequencies
JPH0854955A (ja) * 1994-08-10 1996-02-27 Fujitsu Ltd クロック信号発生回路

Also Published As

Publication number Publication date
JP2001051747A (ja) 2001-02-23
DE10012079A1 (de) 2001-03-01
US6529083B2 (en) 2003-03-04
US20020047748A1 (en) 2002-04-25

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OP8 Request for examination as to paragraph 44 patent law
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP

8327 Change in the person/name/address of the patent owner

Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE

R082 Change of representative

Representative=s name: VON KREISLER SELTING WERNER, DE

R081 Change of applicant/patentee

Owner name: SPANSION LLC (N.D.GES.D. STAATES DELAWARE), US

Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, JP

Effective date: 20140331

Owner name: SPANSION LLC (N.D.GES.D. STAATES DELAWARE), SU, US

Free format text: FORMER OWNER: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP

Effective date: 20140331

Owner name: CYPRESS SEMICONDUCTOR CORP. (N.D.GES.D.STAATES, US

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R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee