CN85108637B - 电子电路器件及其制造方法 - Google Patents
电子电路器件及其制造方法 Download PDFInfo
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- CN85108637B CN85108637B CN85108637A CN85108637A CN85108637B CN 85108637 B CN85108637 B CN 85108637B CN 85108637 A CN85108637 A CN 85108637A CN 85108637 A CN85108637 A CN 85108637A CN 85108637 B CN85108637 B CN 85108637B
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- electronic circuit
- melting point
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- solder
- high melting
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Abstract
在用焊料将诸如半导体或其它元件一类的电子电路元件与用于装配该元件的基板连接中,该焊料包括高熔点焊料部分和体积较小的低熔点焊料,该高熔点焊料部分需经诸如轧制和热处理之类的加工,以便破坏它的铸态结构。经由各低熔点部分,高熔点焊料部分既与电子电路基板相连接又与电子电路元件相连接。这种方法能够使各待接物体之间相互连接而不减损已加工和热处理过的高熔点焊料的延展性和抗疲劳性。这种焊接的方法可以保证高可靠的制造诸如LSI一类的小型化的高密度电路。
Description
本发明是关于一种电子电路器件和加工制造该电子电路器件的方法。本发明由于采用高熔点的焊料(或精制的焊料)和热处理工艺进行机械的或热机械的焊接,从而改进了在诸如半导体芯片一类的电子电路元件部分或其它元件与电路基板之间连接点的可靠性。有关对焊料所需进行的处理将在后面加以介绍。
在电子电路器件领域,为了在机械方面和化学方面保护半导体或元件,并改进电子电路器件的产量和可靠性,已经采用了称之为“表面装配”(surface mounting)的多种方法。其中有一种方法叫做高密度装配法,如图1所示。这种方法是采用精制的焊料3通过电极4和5把半导体芯片1与面朝半导体芯片1的基板2的周围端面连接起来(参看U.S.专利NO.3871014或日本专利公报NO 28735/1968)。在这种方法中,利用比电极4和5熔化得充分的焊料的浸润和扩散作用,使半导体芯片1和电路基板2相互连接。既然需把焊料完全地熔化,那未在该焊料的冷凝阶段,便往往引起合金结构分凝,缺陷及余应力一类的不良结果。因此焊料3具有低延展性的铸态结构。具有此类铸态结构的焊料3相对于外力的延展率低,并产生非均匀变形,这会导致各种应力而使该焊料3产生断裂的一系列问题,而且各种应力在较短的使用期间便会产生出来,这要归因于该焊料的金属疲劳。
随着日益增长的电子元件小型化和提高大规模集成(LSI)的装配密集度的发展趋势,有关器件内部焊接的这样一个问题已变得更为重要。
因此,解决上述问题是本发明的一个目的,同时提供一种实现高可靠焊接的电子电路器件的方法,以及一种制造这种电子电路器件的方法。
为了实现这一目的,本发明具有的特点是,通过对焊料进行轧制和热处理,使其延展性得以大大改善;并且借助于利用该精制焊料的延展性和韧性,将这种焊料成形与焊接处相适应的形状。同时在诸如半导体芯片一类的元件和基板之间采用具有低熔点焊料的焊接点,在一种不致使精制焊料熔化的低温下,通过局部焊接将精制焊料与该低熔点的焊接点连接起来。
此外,本发明提供了一种用于实现本发明的焊接的装置,这样就能够进行高密度电子电路器件的大批量生产。
关于附图的简要介绍
图1是一种常规电子电路器件的透视图;
图2分别表示根据本发明的焊料和现有技术中的焊料的抗拉强度特性曲线;
图3(a)和图3(b)是根据本发明的精制焊料和常规铸制焊料的显微照片;
图4是一种根据本发明的Pb-Sn合金的金相图;
图5是一种Pb-In合金的金相图;
图6是一种Pb-Sb合金的金相图;
图7是根据本发明的一种电子电路器件的实施方案的透视图;
图8是如图7所示的取沿线A-A′面的剖视图;
图9(a)至图9(d)是说明图7所示的电子电路器件各加工步骤的剖视图;
图10是本发明另一种实施方案的陶瓷封装器件的剖视图;
图11是电阻的表面装配元件的剖视图;
图12(a)至图12(d)是说明供给精制焊料各步骤的透视图;
图13是根据本发明的电子电路器件的又一种实施方案的透视图;及
图14是如图13所示的取沿线A-A′的剖视图;
在本发明中将精制焊料用于连接元件和基板的焊接点是根据下面的现象和原理。许多金属在它们被熔化和凝固的过程中会出现诸如吸留气体、形成缺陷的问题,并且大部分合金在其凝固阶段会形成含有结晶分凝和重力分离的多相铸态结构。由于具有缺陷和多相铸态结构的这一类的金属和合金通常是脆而硬的,所以,当使用它们作为结构的成分时,为了改善韧性和延展性,可以通过轧制或热处理来破坏其铸态结构,使其变为单相结构。然而,由于诸如Pb-Sn或Au-Sn一类的合金焊接点是基于熔接原理,这样一种焊接接点在熔化和凝固过程中必然具有铸态结构,而且与上面所述方案不同,几乎不可能借助轧制或热处理来破坏铸态结构。因此只能使用不加任何处理的脆硬的铸态结构,没有另行的选择余地。
图2表示用Pb-Sn作为原材料的精制焊料样件a′,b′及c′和铸制焊料样件a、b及c的拉伸特性,图中以纵座标表示应力(kg/mm2),横座标表示延展率ξ(%)。铸制焊料样件a、b和c只能通过焊接,冷却和固化工艺才可得到。因此,该焊料样件具有铸糙的缺点,铸制焊料样件的微型结构如图3(a)所示。
相反,为了使铸制焊料样件a、b和c克服铸糙之缺点,使其结构均匀,精制焊料样件a′、b′和c′通过进一步的辅助工艺,即铸制焊料样件a、b和c处理之后,进行轧制和热处理工艺便可以得到。微型结构的一实例如图3(b)所示。
根据该图可以很清楚地看到,有a′、b′及c′任一种组成成分的各种精制焊料都是软的,并显示延展率的改善。这些精制焊料的样件是为做薄拉中试验制做的试件,该试件通过冷轧压缩90%。并在室温下进行了大约一周的热处理来加工制备。图3表示含95Pb/5Sn的铸制焊料样件的结构(如图3(a)和图2中的曲线c所示)与精制焊料样件的结构(如图3(b)和图2中c′所示)的对比。如图3(a)和图3(b)所示,与铸制焊料样件的结构(如图3(a)所示)相比较,在精制焊料样件的结构(如图3(b)所示)中,晶粒更为精细,并且分凝出来的高浓度Sn相呈现出象球墨铸铁的球状。因此,其内部应变也更小。如图2所示,精制焊料样件c′的延展性是铸制焊料样件c的三倍或四倍,这个事实表明轧制工作和热处理在改善金属特性方面的各种效果。
发明者根据上述现象已形成了一种设想,即借助使用上述精制焊料可以得到一种接点,这种接点足以抗金属疲劳以及各种应力造成的问题。换言之,通过仅将精制焊料焊点上的比它有更低熔点的焊料的起连接作用的那一端面熔化来实现理想的连接而不失精制焊料的韧性和延展性,从而保证了连接的高可靠性。此外,可以预料几乎所有的焊料都有这些效果。图4、5和6分别是M.Hansen于1958年公开的Pb-Sn合金、Pb-In合金和Pb-Sb合金的金相图。根据这些图很清楚,所有的合金在冷却和凝固阶段都呈现分凝和多相结构,但可以认为通过加工操作和热处理便可以改善它们的延展性。
本发明的下一个实施方案可以参照图7到图9进行说明。图7是采用按照本发明的连接结构的一种电子电路器件的透视图,而图8是该实施方案沿线A-A′的剖视图。如图7和图8所示,将经过加工处理和成形的精制焊料6经由电极4和5安装在半导体芯片1和基板2之间,将具有比该精制焊料熔点低的焊料(图中未标明)附着在与电极4和5上,以便通过仅仅熔化这种附着上的焊料,将半导体芯片1和基板2相连接。
下面参照图9(a)至图9(d)来描述加工制造该实施方案的一种方法。基板2可以用各种材料制成,并采用适合于该种材料的一种方法,将电极5装置在该基片上。例如,如果基板由氧化铝瓷制成,就要通过印制诸如Ag-Pd或W一类的导电膏并进行烧结来形成电极5。当导电粘膏为W的情况下,还需要进行涂镀Ni处理。通过粘涂焊料后的加热回流、焊料球、真空淀积后的回流或焊料的浸涂,可以在电极5上形成诸如Pb-Sn或Au-Sn的共晶易熔焊料接点7。这样,便构成了电路基板2。使用与焊料接点同样的方法,可以在半导体芯片的电极4上形成低熔点焊接点9。
接着,正如图9(b)中所示的那样,将高熔点的精制焊料接点成形为相应于电极5的某种形状,例如圆形、方形或三角形。精制焊料接点8的形状并非必须相应于电极5的形状。例如,精制焊料8的组成成份为95wt%Pb和5wt%Sn或80wt%Au和20Wt%Sn,这种精制焊料8的形成过程是,通过轧制把溶解和铸制的材料制成压缩量为90%的薄片,而后在温度为50℃的惰性气氛条件下,将它进行两天的热处理。将精制焊料8安置在电路基板上且其位置与低熔点焊料7相同。在这种状态下,给基板适当地加热,仅仅使该低熔点焊料溶化,以便将精制焊料8固定连接在电极5上。这种焊料8的拉伸特性与图2中所示的焊料样件c′基本一致。这时将半导体芯片1适当地安放精制焊料8上,并使低熔点焊料9恰好处于与相对应的精制焊料8相同的位置,而后以稍高于低熔点焊料7的熔点的温度加热,从而把半导体芯片连接到精制焊料8的上端部分。这样便可以得到图9(d)中所示的电子电路器件。在这种实施方案中,精制焊料是直径为0.15mm,长度为0.3mm的圆柱体。使用一个在基板上面按照电极5的图形所成的有许多小孔的不锈钢的掩模,可以将精制焊料8加到电路基板上。以这种方法得到的焊接点实际上是由精制焊料组成的,这是因为精制焊料熔点高,并且它的体积也大,而由于熔化与低温熔点焊料7连接的精制焊料8的那部分面积小的只有20到30μm2。通过每小时循环一次的-50℃至+150℃的温度循环测试,曾经估算过精制焊料的寿命,对于95Pb-5Sn的焊料,精制焊料的寿命是常规铸制焊料的五倍,对于80Au-20Sn的焊料,精制焊料的寿命是常规铸制焊料的两倍。
使用同样的方法,可以将本发明用于陶瓷封装的集成电路(IC)中的表面装配元件、电容器、电阻器或诸如此类的元件。例如,正如图10中所示,可以使用本发明的焊料6经由电极4和5把陶瓷外壳18和基板2相互连接起来。陶瓷外壳的构成包括:在陶瓷基板10中为安置元件的凹槽10a的中部所安置的钼-锰层的金属层12,该钼-锰层需经涂镀镍Ni和涂镀金处理;安置在金属层12上的半导体元件13,通过对已开槽部分以外的陶瓷基板10涂镀钼-锰层所形成的内部引线14;为使内部引线14与半导体元件13连接的,用于引线压焊的金属丝15;以及在陶瓷基板10和其上的密封盖16间进行密封的封装部分17。正如图11所表示的那样,这一发明也适用于使用焊料6经由电极4和5把基座2和一个电容器或者电阻器19相连接。
当需要直径为数百μm的数百个电极时,如在大规模的集成电路连接中,依照其焊料,根据电极加工并热处理过的加焊料方法,已经遇到一些问题。依照本发明如图12(a)所示,为了防止这些电极在精密加工操作中的断裂,首先要用衬上淬火硬化的焊剂21(在不高于100℃的温度条件下变硬)的方法,将精制焊料薄片20增强,然后再将它们固着在玻璃薄板22上或类似的薄片上。这里所使用的淬火硬化的焊剂21如不需要时,可以容易地清除。该增强的材料可以是具有比焊料薄片21熔点低的焊料,该焊料通过轧制被涂镀、淀积或覆盖。接着将焊料薄片21用线切割或用电火花加工切割,并以数百μm的间距分割为大量的焊料小柱体6,如图12(b)所示。将在焊料薄片20下面的淬火硬化过的焊剂薄片向下切割到它的厚度的中点,每个焊料小柱就是在那儿固定的。而后,如图12(c)所示,每个焊料小柱体6的端面与诸如共晶易熔焊料的低熔点焊料23相接触,在此之前,该低熔点焊料23借助于浸涂或类似的方法已经加在相对的元件或半导体晶片1一侧表面上。用这样方法,仅仅使低熔点的焊料23熔化,因而可以将全部电极和元件安全可靠地连接起来。在用诸如异丙基乙醇或三氯乙烯一类的溶剂进行溶解而把淬火硬化的焊剂21清除之后,就可以用低熔点的焊料(图中未标明)把元件或半导体芯片1与电路基板2相连接。这样,可以使元件和电路基板2相互连接而不必一个接一个地溶解为数很多的精致的焊点如图12(d)所示。上面所描述的供给焊料的方法,在大批量生产中是很有效的,因为这种焊料不仅供给了每个元件,还可以供给象具有总体加工出全部电极的Si片整个表面。
下面参照图13和图14描述一种应用于封接电子电路器件的本发明的实施方案。如图13和图14所表示的那样,为了把用焊料24与基板相连接的半导体芯片1或电容器一类的元件密封在电路基板2上,将精制焊料26经由电极4和5安置在一个盖子25和电路基板2的外围边缘部分之间,该盖子用来遮盖在半导体芯片1或电容器一类元件之上的部分,在电极4和5和精制焊料26之间,装入其熔点比精制焊料还低的焊料(图中未标明)。并且仅仅熔化该低熔点焊料,就可以通过局部熔化将盖子25和电路基板2连接起来。在由盖子25、精制焊料26及电路基板2所密封的内部为真空或惰性气氛,用以在化学上保护该元件。
半导体芯片1或电容器一类的元件是用高熔点焊料24最佳方式与电路基板2相连接的,所以在焊封盖子和电路基板2时,焊料24不会熔化。在这一案例中,制造电子电路器件方法与图9所示的方法相同。
此外,本发明还可采用另一种方法,(除异常情况之外)即在图14中,第二种焊料用作高熔点焊料26,第一种焊料则用作低焊点焊料24,在盖子25和电路基板2之间进行密封时,纵然使焊料24熔化。
如上所述,本发明能够利用软质,延展性和抗劳性良好的精制焊料进行半导体和电子电路器件的连接和封接。所以,用简单的结构和易行的操作便可以获得高可靠的电子电路器件。这样一种发明能够大大改进不断追求更高可靠性和更高密集度的平面装配技术,例如,本发明可以促进计算机一类的电子电路器件的功能的提高。
Claims (29)
1、一种电子电路器件,包括:
一种基板;
一种装配在所说的基板上的组合件;及用于将所说的组合件与所说的基板连接的焊料;其特征在于:
所说的焊料包括低熔点的焊料和须经加工及热处理的高熔点焊料;并
经由所说的低熔点焊料使所说的高熔点焊料与所说的基板和所说的组合件相连接。
2、根据权利要求1的一种电子电路器件,其特征在于所说的组合件是一种电子电路元件,所说的基板是一种电子电路基板。
3、根据权利要求1的一种电子电路器件,其特征在于所说的组合件是一种半导体芯片,所说的基板是一种电子电路基板,在该基板上面装配所说的半导体芯片。
4、根据权利要求1的一种电子电路器件,其特征在于将一种电子电路元件装配在所述的电子电路基板上,并以第一种焊料与所说的基板相连接;
用于遮盖所说的电子电路元件的盖子是用第二种焊料与所说的电子电路基板连接的;及
所说的第一和第二种焊料至少有一种由低熔点焊料和须加工及热处理的高熔点焊料构成。
5、用于权利要求1的电子电路器件的制造方法,其特征在于所说的方法包括步骤:
准备包括低熔点焊料和须经加工及热处理的高熔点焊料在内的焊料;
在所说的高熔点焊料的预定部位和所说的基板和待连接的组合件预定部位之间放入所说的低熔点焊料;之后
借助熔化所说的低熔点焊料将所说的高熔点焊料部分连接到待连接的基板和组合件上。
6、根据权利要求5的一种制造电子电路的方法,其特征在于所说的高熔点焊料的预定部位和所说的待连接的基板和组合件的预定部位之间放入所说的低熔点焊料步骤,是通过预先将所说的低熔点焊料熔接在所说的高熔点焊料的所说的预定部位来实现的。
7、根据权利要求5的一种制造电子电路的方法,其特征在于,所说的高熔点焊料的预定部位和所说的待连接的基板和组合件的预定部位之间放所说的低熔点焊料的步骤,是通过预先将所说的低熔点焊料熔接在所说的待连接基板和组合件所说的预定部位来实现的。
8、根据权利要求5的一种制造电子电路器件的方法,其特征在于所说的组合件是一种电子电路元件,而所说的基板是一种电路基板;所说的方法包括在所说的高熔点焊料和所说的电子电路元件之间及在所说的高熔点焊料和所说的电子电路基板之间放入所说的低熔点焊料的步骤和通过在低于所说的高熔点的熔化温度而又能使所说的低熔点焊料熔化温度下加热所说的焊料,使所说的电路元件和所说的电路基板相互连接的步骤。
9、根据权利要求5的一种制造电子电路器件的方法,其特征在于所说的基板是一种电子电路基板,所说的组合件是一个用于遮盖电子电路元件的盖子,并将待连接在电路基板上的电子电路元件装配在所说的电子电路基板上;所说的方法包括在所说的高熔点焊料和所说的盖子之间及在所说的高熔点焊料和所说的电子电路基板之间放入所说的低熔点焊料的步骤和通过在低于所说的高熔点焊料的熔化温度而又能使所说的低熔点焊料熔化的温度下加热所说的焊料,使所说的盖子和所说的电路基板相互连接的步骤。
10、根据权利要求5的一种制造电子器件的方法,其特征在于,所说的方法包括步骤:
将所说的高熔点焊料形成薄片并用一种增强材料薄片层来增强它一个端面,该增强材料薄层在不高于100℃的温度条件下淬火,同时在所说的高熔点焊料低的温度下可熔化。
对已增强过的焊料开槽,从所说的高熔点焊料穿过所说的高熔点焊料部分到所说的薄片的中间点;及
将低熔点焊料附盖在所说的高熔点焊料部分的所说的端面,用该低熔点焊料将待连接的基板和组合件和所说的高熔点焊料部分连接。
11、根据权利要求5的一种制造电子电路器件的方法,其特征在于,所说的方法包括步骤:
将所说的高熔点焊料形成薄片,并用一种增强薄层来增强它的一个端面,该增强薄层在比所说的高熔点焊料低的温度下可熔化;
对已增强的焊料薄片开槽,从所说的高熔点焊料部分穿过所说的高熔点部分到所说的薄片的中间点;及
将低熔点焊料附着在所说的高熔点焊料部分的所说的端面上,并用该低熔点焊料连接待连接的第一基板和组合件和所说的高熔点焊料部分。
除去所说的增强薄层,以及
通过附着在所说高熔点焊料的另一端面,具有低熔点焊料的所说增强薄板的去除,使留下来的高熔点焊料与待连接的第二基板和组合件相连接。
12、根据权利要求5的一种制造电子电路器件的方法,其特征在于,当将所说的基板与电子电路组合件相连接时,借助使用一个多孔的掩模罩,在所说的基板和所说的电子电路组合件之间的预定的位置,加装所说的高熔点焊料,该掩模上的孔是相对于所说的电子电路组合件的导体图形而形成的。
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US7287685B2 (en) | 2004-09-20 | 2007-10-30 | International Business Machines Corporation | Structure and method to gain substantial reliability improvements in lead-free BGAs assembled with lead-bearing solders |
JP4492330B2 (ja) * | 2004-12-07 | 2010-06-30 | パナソニック株式会社 | 電子部品実装構造体およびその製造方法 |
JP4555369B2 (ja) * | 2008-08-13 | 2010-09-29 | 富士通メディアデバイス株式会社 | 電子部品モジュール及びその製造方法 |
FR2953679B1 (fr) * | 2009-12-04 | 2012-06-01 | Thales Sa | Boitier electronique hermetique et procede d'assemblage hermetique d'un boitier |
CN107486651B (zh) * | 2017-08-02 | 2020-10-23 | 中国电器科学研究院股份有限公司 | 一种低温焊料片的制备方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3512051A (en) * | 1965-12-29 | 1970-05-12 | Burroughs Corp | Contacts for a semiconductor device |
US3871014A (en) * | 1969-08-14 | 1975-03-11 | Ibm | Flip chip module with non-uniform solder wettable areas on the substrate |
US3871015A (en) * | 1969-08-14 | 1975-03-11 | Ibm | Flip chip module with non-uniform connector joints |
JPS5116260A (ja) * | 1974-07-31 | 1976-02-09 | Hitachi Ltd | Rosetsuho |
JPS5446365A (en) * | 1977-09-20 | 1979-04-12 | Nippon Electric Co | Hybrid integrated circuit device |
JPS58128749A (ja) * | 1982-01-20 | 1983-08-01 | ノ−ス・アメリカン・スペシヤリテイズ・コ−ポレイシヨン | 電子的半組立部品用接続子 |
JPS59169694A (ja) * | 1983-03-16 | 1984-09-25 | Hitachi Ltd | 半田接着方法 |
US4604644A (en) * | 1985-01-28 | 1986-08-05 | International Business Machines Corporation | Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making |
-
1984
- 1984-10-05 JP JP59208072A patent/JPS6187396A/ja active Granted
-
1985
- 1985-09-24 KR KR1019850006974A patent/KR900000183B1/ko not_active IP Right Cessation
- 1985-10-03 DE DE8585112539T patent/DE3581251D1/de not_active Expired - Lifetime
- 1985-10-03 EP EP85112539A patent/EP0177042B1/en not_active Expired - Lifetime
- 1985-10-04 US US06/784,035 patent/US4673772A/en not_active Expired - Lifetime
- 1985-10-05 CN CN85108637A patent/CN85108637B/zh not_active Expired
Also Published As
Publication number | Publication date |
---|---|
DE3581251D1 (de) | 1991-02-14 |
EP0177042A2 (en) | 1986-04-09 |
JPS6187396A (ja) | 1986-05-02 |
JPH0528000B2 (zh) | 1993-04-22 |
KR900000183B1 (ko) | 1990-01-23 |
CN85108637A (zh) | 1986-07-09 |
EP0177042A3 (en) | 1988-08-17 |
EP0177042B1 (en) | 1991-01-09 |
KR860003756A (ko) | 1986-05-28 |
US4673772A (en) | 1987-06-16 |
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