CN2911960Y - 芯片封装件 - Google Patents

芯片封装件 Download PDF

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Publication number
CN2911960Y
CN2911960Y CN 200620079175 CN200620079175U CN2911960Y CN 2911960 Y CN2911960 Y CN 2911960Y CN 200620079175 CN200620079175 CN 200620079175 CN 200620079175 U CN200620079175 U CN 200620079175U CN 2911960 Y CN2911960 Y CN 2911960Y
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chip
plastic
framework
utility
dao
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Expired - Fee Related
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CN 200620079175
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慕蔚
王永忠
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Xi'an TianSheng Electronics Co., Ltd.
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Tianshui Huatian Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本实用新型公开了一种芯片封装件，以解决现有芯片封装结构存在的散热能力差、压焊金线较长、生产成本较高的问题。本实用新型包括基岛、导电胶、芯片、框架内引脚、框架外引脚、金丝、塑封体，基岛通过导电胶与芯片相连，芯片上的焊盘通过金丝与框架内引脚相接；基岛和框架外引脚与塑封体下表面处于同一平面，芯片上表面、金丝、框架内引脚、框架外引脚上表面被塑封体包围成一整体。本实用新型利用基岛与框架外引脚外露，并且与塑封体下表面处于同一平面，可增强散热性，提高功率因子。本实用新型扩大应用范围，生产成本低。

Description

芯片封装件
技术领域
本实用新型涉及一种芯片封装结构。
背景技术
QFN(无引线四方扁平封装)封装是在90年代中期，随着通讯及便携式小型数码电子产品的产生(数码相机、手机、PC、MP3)而发展起来的、适用于高频、宽带、低噪声、高导热、小体积，高速度等电性要求的中小规模集成电路的封装。QFN和CPS有些相似，但元件底部没有焊球，与PCB的电气连接是通过在PCB焊盘上先印刷焊膏，再将器件自动贴片在PCB板的对应位置，然后经过回流焊形成的焊点来实现的。
通用QFN芯片封装结构包括基岛、导电胶、芯片、框架内引脚、框架外引脚、金丝、塑封体；基岛和框架内引脚都不打弯，并且外露处于同一平面；所以芯片上的焊盘与框架内引脚较远，因此金线也较长，生产成本较高，并且塑封时容易交丝和坍丝。
实用新型内容
本实用新型的目的是提供一种芯片封装件，以解决现有芯片封装结构存在的散热能力差、压焊金线较长、生产成本较高的问题。
本实用新型包括基岛、导电胶、芯片、框架内引脚、框架外引脚、金丝、塑封体，基岛通过导电胶与芯片相连，芯片上的焊盘通过金丝与框架内引脚相接；所述基岛和框架外引脚与塑封体下表面处于同一平面，芯片上表面、金丝、框架内引脚、框架外引脚上表面被塑封体包围成一整体。
本实用新型利用基岛与框架外引脚外露，并且与塑封体下表面处于同一平面，可增强散热性，提高功率因子。本实用新型扩大应用范围，生产成本低。
下面结合附图对本实用新型作进一步详细的说明。
附图说明
图1是本实用新型第一种实施方式的结构示意图；
图2是本实用新型第二种实施方式的结构示意图；
图3是本实用新型第三种实施方式的结构示意图。
具体实施方式
本实用新型包括基岛1、导电胶2、芯片3、框架内引脚5、框架外引脚6、金丝7、塑封体9，基岛1通过导电胶2与芯片3相连，芯片3上的焊盘通过压焊金丝7与框架内引脚5相接，形成信号通道。基岛1和框架外引脚6与塑封体9下表面处于同一平面，芯片3上表面、金丝7、框架内引脚5、框架外引脚6上表面被塑封体9包围成一整体。
可增强散热性，提高功率因子。
图1示出了本实用新型的第一种实施方式，框架内引脚5的顶端弯曲与基岛1平行，框架内引脚5的顶端位于塑封体9的中心；用以提高塑封料与框架(电路)内引脚的结合牢度，并且可缩短金丝的长度，节约成本。
图2示出了本实用新型的第二种实施方式，框架内引脚5的顶端弯曲与基岛1平行，框架内引脚5的顶端位于塑封体9的中心；基岛1底部开有环形槽16，槽形部分覆盖有塑封料并与塑封体9相连；既可阻止溢料向基岛表面渗透，又可增强基岛与塑封料的结合牢度。
图3示出了本实用新型的第三种实施方式，基岛1底部开有环形槽16；框架外引脚6底部开有长方形槽17，槽形部分覆盖有塑封料并与塑封体9相连；既增加了塑封体与基岛、框架(电路)外引脚的结合牢度，又可防止溢料向基岛和框架(电路)外引线6底面渗透。

Claims (4)

1、一种芯片封装件，包括基岛、导电胶、芯片、框架内引脚、框架外引脚、金丝、塑封体，基岛通过导电胶与芯片相连，芯片上的焊盘通过金丝与框架内引脚相接；其特征在于：所述基岛(1)和框架外引脚(6)与塑封体(9)下表面处于同一平面，芯片(3)上表面、金丝(7)、框架内引脚(5)、框架外引脚(6)上表面被塑封体(9)包围成一整体。
2、根据权利要求1所述的芯片封装件，其特征在于：所述框架内引脚(5)的顶端弯曲与基岛(1)平行，框架内引脚(5)的顶端位于塑封体(9)的中心。
3、根据权利要求1所述的芯片封装件，其特征在于：所述框架内引脚(5)的顶端弯曲与基岛(1)平行，框架内引脚(5)的顶端位于塑封体(9)的中心；基岛(1)底部开有环形槽(16)，槽形部分覆盖有塑封料并与塑封体(9)相连。
4、根据权利要求1所述的芯片封装件，其特征在于：所述基岛(1)底部开有环形槽(16)；框架外引脚(6)底部开有长方形槽(17)，槽形部分覆盖有塑封料并与塑封体(9)相连。
CN 200620079175 2006-06-13 2006-06-13 芯片封装件 Expired - Fee Related CN2911960Y (zh)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101533038B (zh) * 2009-04-11 2011-06-29 叶隆盛 一种测试座
CN114068468A (zh) * 2021-07-27 2022-02-18 杰华特微电子股份有限公司 引线框架及封装结构
CN115513161A (zh) * 2021-06-07 2022-12-23 江苏长电科技股份有限公司 引脚折弯qfn封装结构及其制作方法
CN115513162A (zh) * 2021-06-07 2022-12-23 江苏长电科技股份有限公司 引脚折弯qfn封装结构及其制作方法
WO2023098266A1 (zh) * 2021-11-30 2023-06-08 广州金升阳科技有限公司 模块电源的引脚结构和模块电源

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101533038B (zh) * 2009-04-11 2011-06-29 叶隆盛 一种测试座
CN115513161A (zh) * 2021-06-07 2022-12-23 江苏长电科技股份有限公司 引脚折弯qfn封装结构及其制作方法
CN115513162A (zh) * 2021-06-07 2022-12-23 江苏长电科技股份有限公司 引脚折弯qfn封装结构及其制作方法
CN114068468A (zh) * 2021-07-27 2022-02-18 杰华特微电子股份有限公司 引线框架及封装结构
WO2023098266A1 (zh) * 2021-11-30 2023-06-08 广州金升阳科技有限公司 模块电源的引脚结构和模块电源

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