CN2879425Y - 高压元件 - Google Patents
高压元件 Download PDFInfo
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- CN2879425Y CN2879425Y CNU2005201366416U CN200520136641U CN2879425Y CN 2879425 Y CN2879425 Y CN 2879425Y CN U2005201366416 U CNU2005201366416 U CN U2005201366416U CN 200520136641 U CN200520136641 U CN 200520136641U CN 2879425 Y CN2879425 Y CN 2879425Y
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- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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Abstract
一种高压元件,包括数个隔离结构、一个第一导电类型掺杂区、至少二个第二导电类型掺杂区、至少二个隔离区、一个栅极结构与一个第二导电类型源极区/漏极区。隔离结构配置于一基底中。第一导电类型掺杂区配置于这些隔离结构之间的基底中。二个第二导电类型掺杂区分别配置于第一导电类型掺杂区两侧的基底中。隔离区配置于第一导电类型掺杂区与第二导电类型掺杂区之间的基底中。栅极结构配置于二个第二导电类型掺杂区之间的基底上。第二导电类型源极区/漏极区配置于栅极结构两侧的基底中。由于利用了上述各掺杂区来代替常用的接合区以及漂移区,并以各掺杂区之间的距离来设定二源极与漏极区的击穿电压,因此便于用来设计不同规格的高压元件。
Description
技术领域
本实用新型涉及一种半导体元件,且特别是涉及一种高压元件。
背景技术
高压元件,顾名思义就是一种可以耐较高偏压的元件,意即高压元件之击穿电压值(Breakdown Voltage)会较一般元件高。现有的高压元件主要是利用隔离层的形成、加大源极与漏极区和栅极之间距、或是在隔离层下方的漂移区与源极与漏极区下方的接合区(Grade Region)进行轻离子掺杂(LightlyDoped),以提高源极与漏极区的结击穿电压,继之使高压元件在高电压的状况下,仍能正常运作。
图1A所绘示为现有一种高压元件的剖面示意图。此高电压元件系在基底100上,先形成多晶硅栅极结构103,然后,在基底100中形成双扩散漏极(Double Diffused Drain,DDD)结构104。此双扩散漏极结构104包括源极区/漏极区104a以及接合区104b。其中接合区104b是用以减轻热电子效应(Hot Electron Effect),藉以提高源极与漏极区104a接电的击穿电压。
图1B所绘示为现有另一种高压元件的剖面示意图。在图1B中,构件与图1A相同者给予相同的标号。在图1B所绘示的高压元件中,在栅极结构103与源极与漏极区104a之间形成有隔离结构106,而且在隔离结构106下方形成有漂移区(Drift Region)108。隔离结构106及漂移区108也是用来减轻热电子效应,以提高源极区/漏极区104a接电的击穿电压。
然而,为了形成如接合区104b与漂移区108等构件来调整击穿电压,则必须个别进行掺杂工艺。而且,击穿电压值的规格或种类愈多,这种掺杂工艺的数量就随之愈大,而造成工艺复杂,且制造成本难以降低。
实用新型内容
本实用新型的目的是提供一种高压元件,以达到不同的高压元件的规格需求。
本实用新型提供一种高压元件。此高压元件是由数个隔离结构、第一导电类型掺杂区、至少二第二导电类型掺杂区、至少二隔离区、栅极结构以及第二导电类型源极区/漏极区所构成。数个隔离结构配置于一基底中;第一导电类型掺杂区配置于这些隔离结构之间的基底中;二第二导电类型掺杂区分别配置于第一导电类型掺杂区两侧的基底中;二隔离区配置于第一导电类型掺杂区与二第二导电类型掺杂区之间的基底中;栅极结构配置于二第二导电类型掺杂区之间的基底上;第二导电类型源极区/漏极区配置于栅极结构两侧的基底中。
在本实用新型之一实施例中,上述之高压元件之第一导电类型掺杂区与二第二导电类型掺杂区的距离在0.1至3微米之间。
在本实用新型之一实施例中,上述之高压元件之第一导电类型掺杂区与二第二导电类型掺杂区的距离为0.5微米。
在本实用新型之一实施例中,上述之高压元件之栅极结构设置于隔离结构之间的基底上,第二导电类型源极区/漏极区设置于隔离结构外侧之基底中。
在本实用新型之一实施例中,上述之第一导电类型是P型,第二导电类型是N型。或者,第一导电类型是N型,第二导电类型是P型。
由于本实用新型的高压元件可以利用上述各掺杂区来代替现有技术的接合区(Grade Region)以及漂移区(Drift)的设置,并以各掺杂区之间的距离来设定二源极与漏极区接电的击穿电压,因此便于用来设计不同规格的高压元件,以达到各种击穿电压值的需求。
附图说明
为让本实用新型之上述和其它目的、特征和优点能更明显易懂,下文特举优选实施例,并配合附图作详细说明如下。
图1A所绘示为现有一种高压元件的剖面示意图。
图1B所绘示为现有另一种高压元件的剖面示意图。
图2A至图2E是依据本实用新型一实施例所绘示的一种半导体元件的制造流程剖面示意图。
图3A所绘示为高压元件区201a的透光区图案未变更前的光掩模207与光掩模215剖面示意图。
图3B所绘示为高压元件区201a的透光区图案变更后的光掩模207与光掩模215的剖面示意图。
图4A与图4B为分别绘示本实用新型一实施例的高压元件的剖面示意图。
主要元件符号说明
100、200、300:基底
103、222、224a、224b、322:栅极结构
104:双扩散漏极结构
104a、236、238、240、336:源极区/漏极区
104b:接合区
106、203、303:隔离结构
108:漂移区
201a:高压元件区
201b:低压元件区
204a、212a、304、312:掺杂区
204b、212b:阱区
206、214:光致抗蚀剂层
206a、214a:曝光部分
206b、214b:图案化光致抗蚀剂层
207、215:光掩模
208、216:透光区图案
210、218:掺杂工艺
221、321:隔离区
222、224a、224b、322:栅极结构
226、326:间隙壁
228、234a、234b、328:栅介电层
230、232a、232b、330:栅极
d1、d2、s1、s2:距离
具体实施方式
图2A至图2E是依据本实用新型一实施例所绘示的一种半导体元件的制造流程剖面示意图。
请参照图2A,提供基底200。此基底200可分为高压元件区201a与低压元件区201b。之后,于基底200中形成数个隔离结构203。隔离结构203的制造方法例如是浅沟槽隔离工艺。隔离结构203的材质例如是氧化硅。之后,于基底200上形成一层光致抗蚀剂层206。此光致抗蚀剂层206的材质例如是正光致抗蚀剂。然后,使用光掩模207进行曝光,而于光致抗蚀剂层206中形成曝光部分206a。在图2A中,光掩模207的透光区图案208以斜线区域表示。
接着,请参照图2B,进行显影工艺,以移除光致抗蚀剂层206之曝光部分206a,而形成图案化光致抗蚀剂层206b。然后,以图案化光致抗蚀剂层206b为罩幕,进行掺杂工艺210,于高压元件区201a的基底200中形成掺杂区204a,并于低压元件区201b的基底200中形成阱区204b。掺杂区204a与阱区204b例如是掺杂P型掺质。掺杂区204a与阱区204b的形成方法例如是离子植入法。
接着,请参照图2C,移除图案化光致抗蚀剂层206b。移除除图案化光致抗蚀剂层206b的方法例如是进行灰化(Ashing)工艺与RCA溶液的清洗工艺。然后,于基底200上形成另一层光致抗蚀剂层214。此光致抗蚀剂层214的材质例如是正光致抗蚀剂。然后,使用光掩模215进行曝光,而于光致抗蚀剂层214中形成曝光部分214a。在图2C中,光掩模215的透光区图案216以斜线区域表示。
之后,请参照图2D,进行显影工艺,移除光致抗蚀剂层214之曝光部分214a,而形成图案化光致抗蚀剂层214b。接着,以图案化光致抗蚀剂层214b为罩幕,进行掺杂工艺218,于高压元件区201a的基底200中形成至少二个掺杂区212a,并于低压元件区201b中形成阱区212b。在高压元件区201a中,掺杂区212a设置于掺杂区204a两侧的基底200中。掺杂区212a与阱区212b例如是掺杂N型掺质。此外,在掺杂区204a与二个掺杂区212a之间的基底200为隔离区221。隔离区221的大小,亦即掺杂区204a与掺杂区212a的距离d1,其例如在0.1至3微米之间,优选为0.5微米。在本实用新型中,所谓的隔离区221是指隔离掺杂区204a与二个掺杂区212a之间的区域,此隔离区221为基底200的一部份。
接着,请继续参照图2E,去除图案化光致抗蚀剂层214b。去除图案化光致抗蚀剂层214b的方法例如是进行灰化(Ashing)工艺与RCA溶液的清洗工艺。然后,在高压元件区201a中,于二掺杂区212a之间的基底200上形成栅极结构222,并在低压元件区201b的阱区204b与阱区212b上分别形成栅极结构224a与栅极结构224b。栅极结构222包括栅介电层228以与门极230。栅极结构224a包括栅极232a与栅介电层234a。栅极结构224b包括栅极232b与栅介电层234b。
栅极结构222、224a、224b的形成方法例如是先于高压元件区201a与低压元件区201b的基底200上分别形成一层厚度不同的介电层,此二层介电层之材质例如是氧化硅。然后,以化学气相沈积法于基底200上形成一层导体层,此导体层之材质例如是掺杂多晶硅。接着,图案化导体层与此二介电层而形成栅极结构222、224a、224b。当然,也可以视实际需要而于栅极结构222、栅极结构224a、栅极结构224b之侧壁形成间隙壁226。间隙壁226的形成方法例如是先于基底200上以化学气相沈积法形成一层介电层,其材质例如是氮化硅,然后进行一非等向性蚀刻工艺,移除部分介电层而形成之。
继之,于栅极结构222两侧的掺杂区212a中形成一源极区/漏极区236,并于栅极结构224a两侧的阱区204b中形成源极区/漏极区238。然后,于栅极结构224b两侧的阱区212b中形成源极区/漏极区240。源极区/漏极区236、238与240的形成顺序并不限定。源极区/漏极区236、238与240的形成方法与一般的互补式金氧半导体工艺相同,在此不再赘述。
接着,对上述实施例中所使用的光掩模207与光掩模215进行说明。一般而言,在现有的互补式金氧半导体工艺中,在制作P型阱区与N型阱区时,所使用的光掩模上的透光区图案是反相(Reverse Tone)的。亦即,用于形成P型阱区与N型阱区的图案化光致抗蚀剂层是互补的图案。在本实施例中,所使用的光掩模207与光掩模215在低压元件区201b的透光区图案是反相(Reverse Tone)。然而,在高压元件区201a中,由于掺杂区204a与掺杂区212a之间配置有隔离区221。因此,光掩模207与光掩模215在高压元件区201a的透光区图案则需要改变。
图3A所绘示为高压元件区201a的透光区图案未变更前的光掩模207与光掩模215剖面示意图。图3B所绘示为高压元件区201a的透光区图案变更后的光掩模207与光掩模215的剖面示意图。其中,透光区图案是以斜线表示。如图3A所示,光掩模215的透光区图案与与光掩模207的图案是互补的。因此,使用图3A所示的光掩模207及光掩模215进行阱区工艺时,在低压元件区201b形成的阱区204b与阱区212b会彼此相邻。同样的,高压元件区201a形成的掺杂区204a与二个掺杂区212a亦会彼此相邻,而无法在掺杂区204a与二掺杂区212a之间分别形成隔离区221。因此,在设计光掩模时,如图3B所示,使光掩模207与光掩模215用于形成低压元件区的图案维持不变,在高压元件区的图案则使透光区图案的边缘分别向内缩减一相同或不同的距离。举例来说,光掩模207的透光区图案的边缘分别往内缩一距离s1;光掩模215的透光区图案的边缘分别往内缩一距离s2。如此,在高压元件区201a形成的掺杂区204a与二个掺杂区212a则会彼此相距一距离,而在掺杂区204a与二掺杂区212a之间分别形成隔离区221。隔离区221的大小会由距离s1及s2来决定。当然,在光掩模的设计上,并不一定要使光掩模207或光掩模215两者的透光区图案的边缘都往内缩,也可以使光掩模207或光掩模215其中之一的透光区图案的边缘往内缩。
在本实用新型的半导体元件制造方法中,由于可以将高压元件的掺杂区与低压元件的阱区整合制作,而不需要分别制作高压元件的各种掺杂区,因此可以降低成本,并减少工艺所需的周期时间(Cycle Time)。特别是省略了许多光掩模设计与光刻工艺的步骤,可以增加产能。此外,藉由控制隔离区221的大小,亦即掺杂区204a与掺杂区212a的距离d1,而可以达到各种击穿电压值的需求。
图4A与图4B为分别绘示本实用新型一实施例的高压元件的剖面示意图。
请参照图4A,本实用新型的高压元件例如是制作于基底300上。此高压元件包括数个隔离结构303、掺杂区304、二个掺杂区312、隔离区321、栅极结构322与源极区/漏极区336所构成。
隔离结构303配置于基底300中,隔离结构303例如是浅沟槽隔离结构,其材质例如是氧化硅。
此外,掺杂区304配置于隔离结构303之间的基底300中。掺杂区304例如是P型的掺杂区或N型的掺杂区。掺杂区312配置于掺杂区304两侧的基底300中,掺杂区312例如是N型的掺杂区或P型的掺杂区。亦即,掺杂区304与掺杂区312的导电类型态相反。此外,掺杂区304与掺杂区312之间的距离d2例如在0.1至3微米之间,此距离d2优选为0.5微米。另外,至少二个隔离区321,配置于掺杂区304与二掺杂区312之间的基底300中。掺杂区304与312之间的距离d2决定隔离区321的大小,并可以决定高压元件的击穿电压值。
栅极结构322配置于二掺杂区312之间的基底300上。栅极结构322包括栅介电层328以与门极330。栅介电层328之材质例如是氧化硅,栅极330之材质例如是掺杂多晶硅。源极区/漏极区336配置于栅极结构两侧的基底300中。源极区/漏极区336与掺杂区312的导电类型态相同。另外也可以视实际需要而于栅极结构322侧壁设置间隙壁326。间隙壁326之材质例如是氮化硅。
请参照图4B,在其中构件与图4A相同者给予相同的标号,并省略其详细的说明。在此只针对不同点进行说明。如图3B所示,栅极结构322形成于隔离结构303之间的基底300上,源极区/漏极区336配置于部分隔离结构303外侧的基底300中。
由于本实用新型的高压元件可以利用上述各掺杂区来代替现有技术的接合区(Grade Region)以及漂移区(Drift)的设置,并以各掺杂区之间的距离来设定二源极与漏极区接电的击穿电压,因此便于用来设计不同规格的高压元件,以达到各种击穿电压值的需求。
虽然本实用新型已结合优选实施例揭露如上,然而其并非用以限定本实用新型,本领域的技术人员在不脱离本实用新型之精神和范围内,可作些许的更动与润饰,因此本实用新型的保护范围包括这些更动与润饰等变形形式。
Claims (6)
1.一种高压元件,其特征在于包括:
多个隔离结构,配置于基底中;
第一导电类型掺杂区,配置于该些隔离结构之间的该基底中;
至少二第二导电类型掺杂区,分别配置于该第一导电类型掺杂区两侧的该基底中;
至少二隔离区,配置于该第一导电类型掺杂区与该二第二导电类型掺杂区之间的该基底中;
栅极结构,配置于该二第二导电类型掺杂区之间的该基底上;以及
第二导电类型源极区/漏极区,配置于该栅极结构两侧的该基底中。
2.如权利要求1所述的高压元件,其特征在于该第一导电类型掺杂区与该二第二导电类型掺杂区的距离在0.1至3微米之间。
3.如权利要求1所述的高压元件,其特征在于该第一导电类型掺杂区与该二第二导电类型掺杂区的距离为0.5微米。
4.如权利要求1所述的高压元件,其特征在于该栅极结构设置于该隔离结构之间的该基底上;以及
该第二导电类型源极区/漏极区,设置于该隔离结构外侧之该基底中。
5.如权利要求1所述的高压元件,其特征在于该第一导电类型是P型,该第二导电类型是N型。
6.如权利要求1所述的高压元件,其特征在于该第一导电类型是N型,该第二导电类型是P型。
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US7851317B2 (en) | 2007-05-29 | 2010-12-14 | Dongbu Hitek Co., Ltd. | Method for fabricating high voltage drift in semiconductor device |
CN101752365B (zh) * | 2008-12-04 | 2012-04-25 | 台湾积体电路制造股份有限公司 | 集成电路结构 |
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US8420488B2 (en) * | 2007-09-11 | 2013-04-16 | United Microelectronics Corp. | Method of fabricating high voltage device |
US8492835B1 (en) | 2012-01-20 | 2013-07-23 | United Microelectronics Corporation | High voltage MOSFET device |
US9219146B2 (en) * | 2013-12-27 | 2015-12-22 | Monolithic Power Systems, Inc. | High voltage PMOS and the method for forming thereof |
TWI685978B (zh) * | 2019-01-04 | 2020-02-21 | 力晶積成電子製造股份有限公司 | 半導體元件及其製造方法 |
TWI747235B (zh) * | 2020-04-16 | 2021-11-21 | 世界先進積體電路股份有限公司 | 高壓半導體裝置 |
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US6096610A (en) * | 1996-03-29 | 2000-08-01 | Intel Corporation | Transistor suitable for high voltage circuit |
EP0975020B1 (en) * | 1998-07-22 | 2009-02-11 | STMicroelectronics S.r.l. | Method for manufacturing electronic devices and corresponding devices comprising HV transistors and LV transistors with salicided junctions |
US6451655B1 (en) * | 1999-08-26 | 2002-09-17 | Stmicroelectronics S.R.L. | Electronic power device monolithically integrated on a semiconductor and comprising a first power region and at least a second region as well as an isolation structure of limited planar dimension |
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US7851317B2 (en) | 2007-05-29 | 2010-12-14 | Dongbu Hitek Co., Ltd. | Method for fabricating high voltage drift in semiconductor device |
CN101315896B (zh) * | 2007-05-29 | 2012-07-18 | 东部高科股份有限公司 | 半导体元件中高压漂移的制造方法 |
CN101752365B (zh) * | 2008-12-04 | 2012-04-25 | 台湾积体电路制造股份有限公司 | 集成电路结构 |
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