CN218887172U - Photoelectronic chip packaging structure - Google Patents
Photoelectronic chip packaging structure Download PDFInfo
- Publication number
- CN218887172U CN218887172U CN202222674785.3U CN202222674785U CN218887172U CN 218887172 U CN218887172 U CN 218887172U CN 202222674785 U CN202222674785 U CN 202222674785U CN 218887172 U CN218887172 U CN 218887172U
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- CN
- China
- Prior art keywords
- frame
- heat conduction
- heat
- hole
- heat dissipation
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- Expired - Fee Related
Links
- 238000004806 packaging method and process Methods 0.000 title abstract description 18
- 230000017525 heat dissipation Effects 0.000 claims abstract description 32
- 230000005693 optoelectronics Effects 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 6
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 3
- 229920005989 resin Polymers 0.000 claims description 3
- RMAQACBXLXPBSY-UHFFFAOYSA-N silicic acid Chemical compound O[Si](O)(O)O RMAQACBXLXPBSY-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000012943 hotmelt Substances 0.000 abstract description 4
- 238000009434 installation Methods 0.000 abstract description 2
- 210000001503 joint Anatomy 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model discloses a photoelectron chip packaging structure, including backing plate and spacing post, the top surface of backing plate is provided with spacing post, and the top of backing plate installs the heat dissipation frame, the inside through-hole that is provided with of frame of heat dissipation frame, and through-hole and spacing post interconnect, the heat conduction frame is installed to the top of heat dissipation frame, and the frame of heat conduction frame has seted up the pin groove, the frame bottom surface of heat conduction frame is provided with first reference column, and first reference column and through-hole interconnect, the frame top surface of heat conduction frame is provided with the second reference column, and the shielding layer is installed to the top of heat conduction frame. This photoelectron chip packaging structure, heat conduction frame can assemble fixed work through first reference column and second reference column with heat dissipation frame and shielding layer, and the structure of convenience each other carries out accurate counterpoint work to do benefit to the follow-up hot melt fixed connection that carries on, make things convenient for whole packaging structure's installation.
Description
Technical Field
The utility model relates to a chip package technical field specifically is a photoelectronic chip packaging structure.
Background
Photoelectron chip carries out the in-process of processing production, need use packaging structure to carry out the work that the protection is sealed to the chip main part, avoids the chip main part to expose outside, but photoelectron chip packaging structure on the existing market still has following problem:
in the assembling and butting process, the fixed connection during packaging of the optoelectronic chip is not accurately aligned and stabilized, so that the connection part can be deviated and the like, and the whole packaging work is influenced.
Aiming at the problems, the novel design is carried out on the basis of the original optoelectronic chip packaging structure.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a photoelectron chip packaging structure to solve common photoelectron chip packaging structure on the existing market that proposes in the above-mentioned background art, at the in-process of assembling the butt joint, fixed connection when encapsulating the photoelectron chip is accurate counterpoint inadequately and firm, leads to phenomenons such as the junction probably takes place the skew, thereby influences the problem of holistic encapsulation work.
In order to achieve the above purpose, the utility model provides a following technical scheme: the utility model provides a photoelectron chip packaging structure, includes backing plate and spacing post, the top surface of backing plate is provided with spacing post, and the top of backing plate installs heat dissipation frame, the inside through-hole that is provided with of frame of heat dissipation frame, and through-hole and spacing post interconnect, heat conduction frame is installed to heat dissipation frame's top, and heat conduction frame's frame has seted up the pin groove, heat conduction frame's frame bottom surface is provided with first reference column, and first reference column and through-hole interconnect, heat conduction frame's frame top surface is provided with the second reference column, and installs the shielding layer in heat conduction frame's top, the frame bottom surface of shielding layer is provided with the locating hole, and locating hole and second reference column interconnect.
Preferably, the limiting column and the base plate are arranged in an integrated structure, and the top end of the limiting column is arranged in an arc structure.
Preferably, the connection mode of the limiting column and the through hole is clamping connection, and the height of the limiting column is smaller than half of the height of the through hole.
Preferably, the heat dissipation frame is connected with the pad and the heat conduction frame in a hot melt manner, the length and the width of the heat dissipation frame are equal to those of the pad, and the heat dissipation frame is made of a heat conduction resin material.
Preferably, the heat-conducting frame is distributed with pin grooves at equal intervals, the length and the width of the heat-conducting frame are equal to those of the heat-radiating frame, and the heat-conducting frame is made of a silicic acid gel material.
Preferably, the first positioning column and the second positioning column are connected with the heat conduction frame in an integrated structure, and the first positioning column is connected with the through hole in a clamping manner.
Preferably, the second positioning columns are distributed on the heat conduction frame at equal intervals, and the second positioning columns are connected with the positioning holes in a clamping manner.
Preferably, the connection mode of the shielding layer and the heat conduction frame is hot melt connection.
Compared with the prior art, the beneficial effects of the utility model are that: the packaging structure of the photoelectronic chip comprises a substrate,
1. the heat conducting frame can be used for conducting heat, and the heat radiating frame can be used for radiating heat, so that the heat buffering work of the subsequent internal optoelectronic chip during working operation is improved, and the overall working efficiency is improved;
2. the heat conduction frame can be assembled and fixed with the heat dissipation frame and the shielding layer through the first positioning column and the second positioning column, and the structure between each other is convenient to carry out accurate alignment work, so that the follow-up hot melting fixed connection is facilitated, and the installation of the whole packaging structure is facilitated.
Drawings
FIG. 1 is a schematic view of the overall three-dimensional structure of the present invention;
FIG. 2 is a schematic view of the overall front cross-sectional structure of the present invention;
FIG. 3 is an enlarged schematic view of the structure at A in FIG. 2 according to the present invention;
fig. 4 is a schematic view of the three-dimensional structure of the heat-conducting frame of the present invention.
In the figure: 1. a base plate; 2. a limiting column; 3. a heat dissipation frame; 4. a through hole; 5. a thermally conductive frame; 6. a lead groove; 7. a first positioning post; 8. a second positioning column; 9. a shielding layer; 10. and (7) positioning the holes.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1-4, the present invention provides a technical solution: the utility model provides a photoelectronic chip packaging structure, including backing plate 1 and spacing post 2, the top surface of backing plate 1 is provided with spacing post 2, and the top of backing plate 1 installs heat dissipation frame 3, the inside through-hole 4 that is provided with of frame of heat dissipation frame 3, and through-hole 4 and spacing post 2 interconnect, heat conduction frame 5 is installed to the top of heat dissipation frame 3, and heat conduction frame 5's frame has seted up pin groove 6, heat conduction frame 5's frame bottom surface is provided with first reference column 7, and first reference column 7 and through-hole 4 interconnect, heat conduction frame 5's frame top surface is provided with second reference column 8, and heat conduction frame 5's top installs shielding layer 9, shielding layer 9's frame bottom surface is provided with locating hole 10, and locating hole 10 and second reference column 8 interconnect.
The limiting column 2 and the base plate 1 are arranged in an integrated structure, and the top end of the limiting column 2 is arranged in an arc-shaped structure, so that the subsequent sliding-in assembly butt joint work of the limiting column 2 is facilitated.
The connection mode of the limiting column 2 and the through hole 4 is clamping connection, the height of the limiting column 2 is smaller than half of the height of the through hole 4, and the base plate 1 and the heat dissipation frame 3 can be accurately aligned through the clamping of the limiting column 2 and the through hole 4.
The connection mode of the heat dissipation frame 3 and the base plate 1 and the heat conduction frame 5 is hot melt connection, the length and the width of the heat dissipation frame 3 are equal to those of the base plate 1, the heat dissipation frame 3 is made of heat conduction resin materials, heat dissipation efficiency is improved, and meanwhile the heat dissipation frame 3 is convenient to assemble and fix with the base plate 1 and the heat conduction frame 5.
The lead grooves 6 are distributed on the heat conduction frame 5 at equal intervals, the length and the width of the heat conduction frame 5 are equal to those of the heat dissipation frame 3, the heat conduction frame 5 is made of a silicic acid gel material, the heat conduction efficiency of the heat conduction frame 5 is improved, and pins can be moved out and butted through the lead grooves 6 subsequently.
The first positioning column 7 and the second positioning column 8 are connected with the heat-conducting frame 5 in an integrated structure, and the first positioning column 7 and the through hole 4 are connected in a clamping manner, so that the heat-conducting frame 5 and the heat-radiating frame 3 can be conveniently and subsequently accurately aligned and assembled.
The second positioning columns 8 are equidistantly distributed on the heat conducting frame 5, and the second positioning columns 8 are connected with the positioning holes 10 in a clamping manner, so that the shielding layer 9 and the second positioning columns 8 can be accurately aligned.
The connection mode of the shielding layer 9 and the heat conduction frame 5 is hot melting connection, so that the whole assembly and fixation are facilitated, and the sealing is convenient.
The working principle is as follows: according to fig. 1-4, after aligning the heat dissipation frame 3 with the backing plate 1, a worker can make the through hole 4 on the heat dissipation frame 3 and the limiting post 2 on the backing plate 1 be in clamping butt joint to facilitate overall sealing work, and subsequently, after aligning the heat conduction frame 5 with the heat dissipation frame 3, make the first positioning post 7 on the heat conduction frame 5 and the through hole 4 on the heat dissipation frame 3 be in clamping butt joint to perform accurate alignment assembly, and then, after aligning the shielding layer 9 with the heat conduction frame 5, the worker can perform accurate alignment assembly work through the clamping butt joint of the positioning hole 10 on the shielding layer 9 and the second positioning post 8 on the heat conduction frame 5, and then perform hot melting fixation to perform overall packaging, and put in advance a chip, and meanwhile, the pin slot 6 provided on the heat conduction frame 5 facilitates the leading-out of pins, which is a working process of the whole device, and the contents not described in detail in this specification belong to the prior art known by professionals in the field.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The utility model provides a photoelectronic chip package structure, includes backing plate (1) and spacing post (2), its characterized in that: the top surface of backing plate (1) is provided with spacing post (2), and the top of backing plate (1) installs heat dissipation frame (3), the inside through-hole (4) that is provided with of frame of heat dissipation frame (3), and through-hole (4) and spacing post (2) interconnect, heat conduction frame (5) are installed to the top of heat dissipation frame (3), and the frame of heat conduction frame (5) has seted up pin groove (6), the frame bottom surface of heat conduction frame (5) is provided with first reference column (7), and first reference column (7) and through-hole (4) interconnect, the frame top surface of heat conduction frame (5) is provided with second reference column (8), and installs shielding layer (9) in the top of heat conduction frame (5), the frame bottom surface of shielding layer (9) is provided with locating hole (10), and locating hole (10) and second reference column (8) interconnect.
2. An optoelectronic chip package as claimed in claim 1, wherein: the limiting column (2) and the base plate (1) are arranged in an integrated structure, and the top end of the limiting column (2) is arranged in an arc-shaped structure.
3. An optoelectronic chip package as claimed in claim 1, wherein: the connection mode of the limiting column (2) and the through hole (4) is clamping connection, and the height of the limiting column (2) is less than half of the height of the through hole (4).
4. An optoelectronic chip package as claimed in claim 1, wherein: the heat dissipation frame (3) is connected with the base plate (1) and the heat conduction frame (5) in a hot melting mode, the length and the width of the heat dissipation frame (3) are equal to those of the base plate (1), and the heat dissipation frame (3) is made of heat conduction resin materials.
5. An optoelectronic chip package as claimed in claim 1, wherein: the heat-conducting frame (5) is provided with pin grooves (6) at equal intervals, the length and the width of the heat-conducting frame (5) are equal to those of the heat-radiating frame (3), and the heat-conducting frame (5) is made of a silicic acid gel material.
6. An optoelectronic chip package as claimed in claim 1, wherein: the first positioning column (7), the second positioning column (8) and the heat conduction frame (5) are connected in an integrated structure, and the first positioning column (7) and the through hole (4) are connected in a clamping manner.
7. An optoelectronic chip package as claimed in claim 1, wherein: the second positioning columns (8) are distributed on the heat conduction frame (5) at equal intervals, and the second positioning columns (8) are connected with the positioning holes (10) in a clamping mode.
8. An optoelectronic chip package as claimed in claim 1, wherein: the shielding layer (9) and the heat conduction frame (5) are connected in a hot melting mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222674785.3U CN218887172U (en) | 2022-10-11 | 2022-10-11 | Photoelectronic chip packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222674785.3U CN218887172U (en) | 2022-10-11 | 2022-10-11 | Photoelectronic chip packaging structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN218887172U true CN218887172U (en) | 2023-04-18 |
Family
ID=85977386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222674785.3U Expired - Fee Related CN218887172U (en) | 2022-10-11 | 2022-10-11 | Photoelectronic chip packaging structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN218887172U (en) |
-
2022
- 2022-10-11 CN CN202222674785.3U patent/CN218887172U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20230418 |