CN212848373U - Wafer packaging heat dissipation mechanism - Google Patents
Wafer packaging heat dissipation mechanism Download PDFInfo
- Publication number
- CN212848373U CN212848373U CN202021861115.7U CN202021861115U CN212848373U CN 212848373 U CN212848373 U CN 212848373U CN 202021861115 U CN202021861115 U CN 202021861115U CN 212848373 U CN212848373 U CN 212848373U
- Authority
- CN
- China
- Prior art keywords
- heat
- conducting
- layer
- heat dissipation
- conducting plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
The utility model discloses a wafer encapsulation heat dissipation mechanism, including heat dissipation layer, first heat-conducting layer and semiconductor substrate, the semiconductor substrate upper surface is provided with the second heat-conducting plate, the semiconductor substrate is provided with the heat conduction through-hole all around, the first heat-conducting layer of heat conduction through-hole bottom fixedly connected with, the semiconductor substrate lower surface is provided with first heat-conducting plate, the inside first heat-conducting post that evenly is provided with of first heat-conducting plate, the one end fixed connection heat dissipation layer of first heat-conducting plate is kept away from to first heat-conducting post. This wafer encapsulation heat dissipation mechanism, the structure sets up rationally, through setting up first heat-conducting layer and second heat-conducting layer, derives the heat of semiconductor substrate, sets up the fin on the second heat-conducting post, increases second heat-conducting post and air area of contact, improves the radiating efficiency, and first heat-conducting post is inside to set up the heat conduction granule, and the absorption heat that can step forward can accelerate thermal volatilizing, the safe operation of assurance wafer chip that can be better promotes the development of wafer chip trade.
Description
Technical Field
The utility model relates to a wafer packaging technology field specifically is a wafer packaging heat dissipation mechanism.
Background
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a function requirement to obtain an independent chip, and the packaging process is as follows: a wafer from a wafer previous process is cut into small chips (Die) through a scribing process, then the cut chips are pasted on small islands of corresponding substrate (Lead frame) frames through glue, and bonding pads (Bond pads) of the chips are connected to corresponding pins (Lead) of the substrate through superfine metal (gold tin copper aluminum) wires or conductive resin to form a required circuit; then, the independent chips are packaged and protected by plastic shells, a series of operations are carried out after plastic packaging, finished product testing is carried out after packaging is completed, along with stacking and accumulation of the chips, the problem of heat dissipation of the chips in the semiconductor packaging structure is more serious originally, the wafers in the existing wafer packaging heat dissipation structure are directly in contact connection with a heat dissipation module so as to achieve the purpose that the heat of the wafers is dissipated through the heat dissipation module, the heat dissipation module is used as a carrier of the wafers and is connected with electrodes and electrode pins, the problems of complex heat dissipation structure, poor heat dissipation efficiency and troublesome packaging and maintenance are caused, and if the wafer packaging heat dissipation structure is not improved, the normal use of the wafer chips can be influenced.
In order to overcome the defects existing in the current market, a technology for improving a wafer packaging heat dissipation structure is urgently needed, so that the safe operation of a wafer chip can be better ensured, and the development of the wafer chip industry is promoted.
SUMMERY OF THE UTILITY MODEL
An object of the utility model is to provide a wafer encapsulation heat dissipation mechanism to wafer is direct to be connected with the thermal module contact among the wafer encapsulation heat radiation structure who proposes in solving above-mentioned background art, passes through the radiating purpose of thermal module in order to reach the heat of wafer, and thermal module is connected by being as electrode and electrode pin as the carrier of wafer promptly, causes that heat radiation structure is more complicated, and the radiating efficiency is not good, encapsulation and the trouble problem of maintenance.
In order to achieve the above object, the utility model provides a following technical scheme: the utility model provides a wafer encapsulation heat dissipation mechanism, includes heat dissipation layer, first heat-conducting layer and semiconductor substrate, the semiconductor substrate upper surface is provided with the second heat-conducting plate, and second heat-conducting plate outward flange and second heat-conducting layer fixed connection, the semiconductor substrate is provided with the heat conduction through-hole all around, and heat conduction through-hole top fixed connection second heat-conducting plate, the first heat-conducting layer of heat conduction through-hole bottom fixedly connected with, semiconductor substrate lower surface is provided with first heat-conducting plate, and first heat-conducting plate outward flange is connected with first heat-conducting layer, the inside first heat-conducting plate that evenly is provided with of first heat-conducting column, and the inside heat conduction granule that is provided with of first heat-conducting column, the one end fixed connection heat dissipation.
Preferably, the thickness of the first heat-conducting plate is consistent with that of the first heat-conducting plate, and the thickness of the second heat-conducting plate is consistent with that of the second heat-conducting plate.
Preferably, the second heat-conducting plate top evenly is provided with the second heat-conducting post, and second heat-conducting post and second heat-conducting plate are hollow structure, and the outside surface cladding of second heat-conducting post has honeycomb fin.
Preferably, the first heat conduction layer, the second heat conduction layer and the heat dissipation layer are all rectangular structures, and the centers of the first heat conduction layer, the second heat conduction layer and the heat dissipation layer are kept in the same vertical direction.
Preferably, the surface area of the upper surface of the heat dissipation layer is larger than the surface areas of the first heat conduction layer and the second heat conduction layer, and heat dissipation holes are uniformly formed in the first heat dissipation layer.
Preferably, the first heat-conducting plate and the second heat-conducting plate are cylindrical structures with the same radius, and the radius of the first heat-conducting plate and the radius of the second heat-conducting plate are both larger than the radius of the wafer chip.
Compared with the prior art, the beneficial effects of the utility model are that: this wafer encapsulation heat dissipation mechanism, the structure sets up rationally, through setting up first heat-conducting layer and second heat-conducting layer, derive the heat of semiconductor substrate, be provided with the heat conduction through-hole between first heat-conducting layer and the second heat-conducting layer, make the heat can not transmit from top to bottom, prevent that the heat from being absorbed once more by the semiconductor, set up the fin on the second heat-conducting post, increase second heat-conducting post and air area of contact, the heat dissipation efficiency is improved, the inside heat conduction granule that sets up of first heat-conducting post, can further absorbed heat, prevent that the heat from too high causing the damage to the semiconductor substrate, the setting of louvre on the heat dissipation layer, thermal volatilizing can accelerate, the safe operation of assurance wafer chip that can be better, promote the development of wafer chip.
Drawings
FIG. 1 is a front view of the structure of the present invention;
FIG. 2 is a schematic top view of the structure of the present invention;
fig. 3 is a schematic view of a second heat-conducting pillar of the present invention.
In the figure: 1. a heat dissipation layer; 2. a first thermally conductive layer; 3. a thermally conductive via; 4. a semiconductor substrate; 5. a second thermally conductive layer; 6. a second heat-conducting plate; 7. a second thermally conductive post; 8. a first heat-conducting plate; 9. heat dissipation holes; 10. a first thermally conductive post; 11. thermally conductive particles; 12. and a heat sink.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.
Referring to fig. 1-3, the present invention provides a technical solution: a wafer packaging heat dissipation mechanism comprises a heat dissipation layer 1, a first heat conduction layer 2 and a semiconductor substrate 4, wherein a second heat conduction plate 6 is arranged on the upper surface of the semiconductor substrate 4, the outer edge of the second heat conduction plate 6 is fixedly connected with a second heat conduction layer 5, heat conduction through holes 3 are arranged on the periphery of the semiconductor substrate 4, the top of each heat conduction through hole 3 is fixedly connected with the second heat conduction plate 6, the bottom of each heat conduction through hole 3 is fixedly connected with the first heat conduction layer 2, a first heat conduction plate 8 is arranged on the lower surface of the semiconductor substrate 4, the outer edge of the first heat conduction plate 8 is connected with the first heat conduction layer 2, a wafer is fully contacted with the first heat conduction plate 8 and the second heat conduction plate 6, the heat dissipation efficiency is improved, the first heat conduction layer 2 and the second heat conduction layer 5 can be connected with electrodes, the heat conduction through holes 3 block up-down transmission of heat, the heat conducting particles 11 are arranged in the first heat conducting column 10, one end of the first heat conducting column 10 far away from the first heat conducting plate 8 is fixedly connected with the heat radiating layer 1, the thickness of the first heat conducting plate 8 is consistent with that of the first heat conducting layer 2, the thickness of the second heat conducting plate 6 is consistent with that of the second heat conducting layer 5, so that heat transmission is facilitated, the second heat conducting column 7 is uniformly arranged above the second heat conducting plate 6, the second heat conducting column 7 and the second heat conducting plate 6 are both in a hollow structure, the outer surface of the second heat conducting column 7 is coated with the honeycomb-shaped heat radiating fins 12, the contact area of the second heat conducting column 7 and air is increased, the heat radiating efficiency is improved, the first heat conducting layer 2, the second heat conducting layer 5 and the heat radiating layer 1 are all in a rectangular structure, the centers of the first heat conducting layer 2, the second heat conducting layer 5 and the heat radiating layer 1 are kept in the, and the inside of the first heat dissipation layer 1 is uniformly provided with heat dissipation holes 9, the first heat conduction plate 8 and the second heat conduction plate 6 are in a cylindrical structure with the same radius, and the radius of the first heat conduction plate 8 and the radius of the second heat conduction plate 6 are both larger than the radius of the wafer chip.
The working principle is as follows: when the wafer packaging heat dissipation mechanism is used, the first heat conduction layer 2 and the second heat conduction layer 5 are arranged, heat of the semiconductor substrate 4 is led out, the heat conduction through holes 3 are formed between the first heat conduction layer 2 and the second heat conduction layer 5, heat can not be transmitted up and down, heat is prevented from being absorbed by the semiconductor substrate 4 again, the radiating fins 12 are arranged on the second heat conduction columns 7, the contact area of the second heat conduction columns 7 and air is enlarged, the heat dissipation efficiency is improved, the heat conduction particles 11 are arranged inside the first heat conduction columns 10, heat can be further absorbed, damage to the semiconductor substrate 4 due to overhigh heat is prevented, the radiating holes 9 are formed in the radiating layer 1, volatilization of heat can be accelerated, and the whole working process of the wafer packaging heat dissipation mechanism is achieved.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (6)
1. A wafer packaging heat dissipation mechanism comprises a heat dissipation layer (1), a first heat conduction layer (2) and a semiconductor substrate (4), and is characterized in that: the heat-conducting structure is characterized in that a second heat-conducting plate (6) is arranged on the upper surface of the semiconductor substrate (4), the outer edge of the second heat-conducting plate (6) is fixedly connected with the second heat-conducting layer (5), heat-conducting through holes (3) are formed in the periphery of the semiconductor substrate (4), the top of each heat-conducting through hole (3) is fixedly connected with the second heat-conducting layer (6), a first heat-conducting layer (2) is fixedly connected with the bottom of each heat-conducting through hole (3), a first heat-conducting plate (8) is arranged on the lower surface of the semiconductor substrate (4), the outer edge of the first heat-conducting plate (8) is connected with the first heat-conducting layer (2), a first heat-conducting column (10) is evenly arranged inside the first heat-conducting column (8), heat-conducting particles (11) are arranged inside the first heat-conducting column (10), and the.
2. The heat dissipation mechanism of claim 1, wherein: the first heat conducting plate (8) and the first heat conducting layer (2) are consistent in thickness, and the second heat conducting plate (6) and the second heat conducting layer (5) are consistent in thickness.
3. The heat dissipation mechanism of claim 1, wherein: second heat-conducting post (7) are evenly provided with above second heat-conducting plate (6), and second heat-conducting post (7) and second heat-conducting plate (6) are hollow structure, and the outside surface cladding of second heat-conducting post (7) has honeycomb fin (12).
4. The heat dissipation mechanism of claim 1, wherein: the first heat conduction layer (2), the second heat conduction layer (5) and the heat dissipation layer (1) are all of rectangular structures, and the centers of the first heat conduction layer (2), the second heat conduction layer (5) and the heat dissipation layer (1) are kept in the same vertical direction.
5. The heat dissipation mechanism of claim 1, wherein: the heat dissipation layer (1) is characterized in that the upper surface area of the heat dissipation layer (1) is larger than the surface areas of the first heat conduction layer (2) and the second heat conduction layer (5), and heat dissipation holes (9) are uniformly formed in the first heat dissipation layer (1).
6. The heat dissipation mechanism of claim 1, wherein: the first heat-conducting plate (8) and the second heat-conducting plate (6) are of cylindrical structures with the same radius, and the radii of the first heat-conducting plate (8) and the second heat-conducting plate (6) are both larger than the radius of the wafer chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021861115.7U CN212848373U (en) | 2021-01-27 | 2021-01-27 | Wafer packaging heat dissipation mechanism |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202021861115.7U CN212848373U (en) | 2021-01-27 | 2021-01-27 | Wafer packaging heat dissipation mechanism |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN212848373U true CN212848373U (en) | 2021-03-30 |
Family
ID=75142720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202021861115.7U Active CN212848373U (en) | 2021-01-27 | 2021-01-27 | Wafer packaging heat dissipation mechanism |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN212848373U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380732A (en) * | 2021-04-22 | 2021-09-10 | 湖南迈克森伟电子科技有限公司 | Optimization design of novel high-performance heat dissipation base |
-
2021
- 2021-01-27 CN CN202021861115.7U patent/CN212848373U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113380732A (en) * | 2021-04-22 | 2021-09-10 | 湖南迈克森伟电子科技有限公司 | Optimization design of novel high-performance heat dissipation base |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8012797B2 (en) | Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries | |
| US8076765B2 (en) | Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors | |
| CN212848373U (en) | Wafer packaging heat dissipation mechanism | |
| CN113937009A (en) | Packaging method of surface-mounted double-sided heat dissipation semiconductor power device | |
| CN210167324U (en) | Chip packaging product | |
| CN210156364U (en) | Layered isolation packaging structure of large-size chip | |
| CN112885804A (en) | Surface-mounted photovoltaic bypass module and packaging process thereof | |
| CN218730911U (en) | Double-sided heat dissipation packaging structure with internal insulation | |
| US8288863B2 (en) | Semiconductor package device with a heat dissipation structure and the packaging method thereof | |
| CN204088301U (en) | Based on the chip packaging device that copper ball flattens in advance | |
| CN1172369C (en) | Semiconductor package with heat radiator | |
| CN210040171U (en) | Chip packaging product | |
| CN210897253U (en) | Semiconductor packaging structure | |
| CN214336701U (en) | Semiconductor chip packaging module structure with low thermal resistance | |
| CN1372317A (en) | Chip heat sink package structure and making method thereof | |
| CN210272320U (en) | Packaging structure for preventing layering | |
| CN1153287C (en) | Semiconductor package with built-in heat dissipating block | |
| CN210182391U (en) | Novel packaging-free diode | |
| CN212625548U (en) | Heat dissipation type semiconductor packaging piece | |
| JP2002033345A (en) | Method for manufacturing resin-sealed semiconductor device | |
| CN114300563B (en) | Photovoltaic module structure and processing technology | |
| CN214588813U (en) | Packaging structure of reverse-bending internal insulation product | |
| KR20000020421A (en) | High heat dissipating chip scale package(csp) and manufacturing method thereof | |
| US20220238425A1 (en) | Semiconductor package structure | |
| CN218385211U (en) | TO-263 double-core copper sheet welding packaging structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |