CN210272320U - Packaging structure for preventing layering - Google Patents
Packaging structure for preventing layering Download PDFInfo
- Publication number
- CN210272320U CN210272320U CN201921693748.9U CN201921693748U CN210272320U CN 210272320 U CN210272320 U CN 210272320U CN 201921693748 U CN201921693748 U CN 201921693748U CN 210272320 U CN210272320 U CN 210272320U
- Authority
- CN
- China
- Prior art keywords
- base island
- chip
- pad
- delamination
- fastener
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a prevent packaging structure of layering, through the process flows such as base plate preparation, chip dress piece, first encapsulation, expose copper lug, drilling, electroplate, secondary encapsulation and support plate strip, adopt the fastener plastic envelope in the plastic envelope, fixed connection between fastener and the base island, thereby increase the area of contact between base island and the plastic envelope body, improve the cohesiveness between the plastic envelope body and the base island, install the fastener in any place that does not influence other electronic component on the base island, the position can be adjusted in a flexible way, on all encapsulation sizes and the chips of different sizes in the chip encapsulation field, the fastener increases the area of contact between base island and the plastic envelope body, improve the heat conduction on the base island, can improve the efficiency of heat energy dissipation on the base island and the chip connected with the base island, effectively avoid producing the phenomenon that the layering breaks away from because of high temperature leads to producing between the material of different thermal expansion coefficients, thereby improving the reliability of the chip package.
Description
Technical Field
The utility model relates to a semiconductor package technical field especially relates to a packaging structure of prevention layering.
Background
With the development of electronic products, semiconductor technology has been widely used to manufacture memory, Central Processing Unit (CPU), Liquid Crystal Display (LCD), Light Emitting Diode (LED), laser diode, and other devices or chip sets.
Since electronic components such as semiconductor components, micro-electromechanical components (MEMS) or optoelectronic components have minute and fine circuits and structures, in order to prevent dust, acid-base substances, moisture, oxygen, etc. from contaminating or eroding the electronic components, thereby affecting their reliability and life, it is necessary to provide the electronic components with related functions such as electrical energy creation, signal transmission, heat dissipation, protection and support, etc. by packaging technology.
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: a wafer from a wafer previous process is cut into small chips (Die) through a scribing process, then the cut chips are pasted on small islands of corresponding substrate (Lead frame) frames through glue, and bonding pads (Bond pads) of the chips are connected to corresponding pins (Lead) of the substrate through superfine metal (gold tin copper aluminum) wires or conductive resin to form a required circuit; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out procedures such as inspection, Test, packaging and the like, and finally warehousing and shipping.
In the field of chip packaging, the adopted packaging materials are more in variety, the physical properties of different materials are different, and particularly the thermal expansion coefficients of different materials are different, so that parts of different materials which are in mutual contact have obvious influence, for a large-size packaging body, the size of a chip is larger, the size of a base island is larger than that of the chip, a layering phenomenon easily occurs in a strict working environment or test after the chip is packaged by a chip packaging piece, particularly, the heat on the chip cannot be timely dissipated, the temperature on the chip and the plastic packaging material can be gathered, the temperature on the chip and the plastic packaging material is not uniformly dispersed, the thermal expansion efficiency is increased, the layering separation phenomenon of the chip and a frame or the base island is more easily caused, and the performance and the effective use of a product are seriously influenced.
SUMMERY OF THE UTILITY MODEL
The utility model discloses just to prior art exist not enough, provide a packaging structure of prevention layering.
In order to solve the above problems, the utility model adopts the following technical proposal:
the utility model provides a packaging structure of prevention layering, includes a plastic envelope body, has at least an electronic component plastic envelope in the plastic envelope body, at least one base island and at least one pin have on the electronic component, the top of pin exposes in the surface of the plastic envelope body, the surface of base island is equipped with at least one fastener, fixed connection between fastener and the base island, and the fastener plastic envelope is in the plastic envelope body.
Furthermore, the fastener comprises a connecting piece with one end connected with the base island, and the other end of the connecting piece is plastically packaged in the plastic package body.
Furthermore, the fastener still includes the ear spare that is used for the solid plastic-sealed body of card, the ear spare with the one end of keeping away from the base island on the connecting piece is connected fixedly.
Furthermore, a chip is arranged on the electronic component, the back face of the chip is attached to the base island, a gasket is arranged in the plastic package body, the gasket is not connected with the base island, the pins are respectively arranged on the base island and the gasket, and the chip and the gasket are connected through a rewiring layer.
Further, the gasket and the base island are located on the same plane and have the same thickness, and the gasket and the pins on the base island are located on the same side of the plane formed by the gasket and the base island.
Further, the pin is an outer pin.
Furthermore, the redistribution layer is parallel to the base island, a sunken table with a hat-shaped cross section is arranged at one end, connected with the gasket, of the redistribution layer, the sunken table protrudes towards the direction of the gasket, and the table top of the sunken table is attached to and fixed with the surface of the gasket.
Furthermore, the base island and the gasket are made of copper metal.
Furthermore, the connecting piece and the ear piece are made of metal capable of being electroplated.
Furthermore, the chip and the base island are in transition connection through a metal transition layer, and the metal transition layer comprises at least one of TiNiAg, TiAu or TiCu.
Compared with the prior art, the utility model, the beneficial effects are as follows:
the utility model provides a packaging structure for preventing layering, adopt fastener plastic envelope in the plastic envelope, fixed connection between fastener and the foundation island, thereby increase the area of contact between foundation island and the plastic envelope, can improve the cohesiveness between the plastic envelope and the foundation island greatly, and design the fastener into the structure of connecting piece and ear spare, the foundation island is connected with the ear spare through the connecting piece, the ear spare only blocks the plastic envelope in the plastic envelope, because of the effect of connecting piece, make the foundation island at chip back or replace between the frame that the foundation island adopted and the plastic envelope when actually using lock, effectively prevent the layering between chip and frame or the foundation island from breaking away from, also prevent the layering between the plastic envelope and foundation island or the frame from breaking away from, and in this structure, the fastener can be installed in any place that does not influence other electronic components on the island, the position can be adjusted in a flexible way, on all encapsulation sizes and the not chip of equidimension that is applicable to the chip package field, because the effect of fastener, increase area of contact between island and the plastic-sealed body, also can improve the heat conduction on the island, thereby make the temperature in the encapsulation body more even, can not produce the phenomenon that temperature deviation is big, also can improve the efficiency that heat energy gived off on the island and the chip of being connected with the island, thereby when reliability test and the practical application in later stage, effectively avoid producing the phenomenon that the layering breaks away from because of high temperature leads to producing between different thermal expansion coefficient's the material, thereby improve the reliability of chip package, promote the performance of chip.
Drawings
Fig. 1 is a schematic step diagram of a packaging process of a delamination prevention packaging structure according to the present invention;
fig. 2 to 9 are process flow diagrams of a delamination prevention package structure according to a first embodiment of the present invention;
fig. 10 is a schematic structural diagram of a delamination prevention package structure according to a first embodiment of the present invention;
FIG. 11 is a structural diagram of a delamination prevention package structure according to the second embodiment;
FIG. 12 is a top view of FIG. 11;
FIG. 13 is a structural diagram of a delamination prevention package structure according to the third embodiment;
FIG. 14 is a top view of FIG. 13;
FIG. 15 is a structural diagram of a delamination prevention package structure according to the fourth embodiment;
FIG. 16 is a top view of FIG. 15;
FIG. 17 is a schematic structural diagram of a delamination prevention package structure according to the fifth embodiment;
fig. 18 is a top view of fig. 17.
Detailed Description
The present invention will now be described in connection with particular embodiments, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar function throughout.
The utility model discloses directional phrase mentioned, for example: upper, lower, left, right, front, rear, inner, outer, front, back, side, etc., are merely directions with reference to the drawings, and the embodiments described below by referring to the drawings and directional terms used are exemplary and are only used for explaining the present invention, and are not to be construed as limiting the present invention. In addition, the present invention provides examples of various specific processes and materials that one of ordinary skill in the art would recognize for other processes and/or other materials to use.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a step of a packaging process of a delamination prevention packaging structure according to the present invention.
The packaging process of the packaging structure for preventing delamination comprises the following steps:
s1: preparing a substrate; s2: chip mounting; s3: first packaging; s4: exposing the copper bump; s5: drilling; s6: electroplating; s7: second encapsulation and S8: and stripping the carrier plate. The above steps are described in detail below with reference to the accompanying drawings and embodiments.
[ EXAMPLES one ]
A package structure for preventing delamination:
referring to fig. 2 to 10, fig. 2 to 9 are process flow diagrams of a first embodiment of a delamination prevention package structure according to the present invention; fig. 10 is a schematic structural diagram of a delamination prevention package structure according to a first embodiment of the present invention.
Regarding step S1: and (4) preparing a substrate.
As shown in fig. 2, fig. 2 is a schematic structural diagram of a substrate and a carrier.
The back side of the substrate a is placed onto a carrier b, which is made of a material including, but not limited to, a metal or alloy plate, a BT material, a FR-4 material, a silicon-based material, an EMC material, a glass material, or a thin film material. The carrier plate b is used for supporting and protecting, the two pins 40 are embedded in the substrate a, exposed on the back of the substrate a, contacted with the carrier plate b and attached, the base island 30 protruding out of the surface of the substrate a and the gasket 60 not contacted with the base island 30 are arranged on the surface of the substrate a far away from the carrier plate b, the base island 30 and the gasket 60 are respectively and electrically connected with the two pins 40 in the substrate a, the base island 30 and the gasket 60 are positioned on the same horizontal plane, have the same thickness and are made of metal materials, and the gasket 60 is a copper gasket.
The substrate a and the carrier plate b are bonded through glue, soluble matters or meltable matters, such as hydrogel, pyrolytic gel or photolytic gel, so that the substrate a and the carrier plate b can be peeled off conveniently in the later period.
Among them, hydrogels (hydrogels) are a very hydrophilic three-dimensional network structure gel which rapidly swells in water and can hold a large volume of water in this swollen state without dissolution, and can swell and hold a large amount of water due to the presence of a crosslinked network, and the amount of water absorption is closely related to the degree of crosslinking. The higher the degree of crosslinking, the lower the water absorption. This property is very much like a soft tissue. The water content in the hydrogel can be as low as a few percent, and can also be as high as 99 percent. The gel is neither a completely solid nor a completely liquid in its aggregate state. The behavior of a solid is that it can maintain a certain shape and volume under certain conditions, and the behavior of a liquid is that a solute can diffuse or permeate from the hydrogel. The hydrogel can be removed by heating in water.
The pyrolytic gel is a solvent adhesive, has certain adhesive force at normal temperature, can play a role in positioning and supporting, can disappear only by heating the temperature to a set temperature, can realize simple stripping, has less residues and does not pollute an adherend.
The photodecomposition glue has certain adhesive force, can play a role in positioning and supporting, can be subjected to photodecomposition reaction after being irradiated by light to be changed into water-soluble glue, and can realize simple stripping.
Regarding step S2: and (5) chip mounting.
As shown in fig. 3, fig. 3 is a schematic diagram of a chip mounting structure.
The back of the chip 21 having completed the BUMP process is loaded on the surface of the base island 30 away from the substrate a (the BUMP process of the chip is mature in technology and common knowledge for those skilled in the art, and is not necessary technical features required for solving the technical problems of the present invention, so detailed description is not given here), the chip 21 and the base island 30 are attached to each other, the active surface of the chip 21 having completed the BUMP process has a copper BUMP 21a, the active surface of the chip 21 faces away from the substrate a, the chip 21 and the base island 30 are transitionally connected by arranging a metal transition layer, and the material of the metal transition layer includes at least one of TiNiAg, TiAu or TiCu.
Because the back of the chip 21 is usually made of pure silicon material and can not be connected with other metals in an infiltration manner, when the chip 21 is mounted on the base island 30, a metal transition layer is arranged between the chip 21 and the base island 30 for excessive connection, so that the connection performance and the conductivity are improved, the phenomenon that the chip 21 is separated from the base island 30 at the later stage to cause the damage of a packaging structure is avoided, and the defective rate is greatly reduced.
Regarding step S3: and (5) packaging for the first time.
As shown in fig. 4, fig. 4 is a schematic structural diagram of the first encapsulation after the chip is mounted.
And performing first encapsulation on the carrier b to form a first plastic package body 10a, wherein the base island 30, the pad 60, the pin 40, the chip 21 and the copper bump 21a are all encapsulated in the first plastic package body 10a and are not in contact with the external atmosphere, and the material of the first plastic package body 10a is any plastic package material known to those skilled in the art, such as a resin material.
Regarding step S4: the copper bump is exposed.
As shown in fig. 5, and with reference to fig. 4, fig. 5 is a schematic structural view illustrating the exposed copper bump on the chip.
The outer surface of the first plastic package body 10a near the copper bump 21a is cut by grinding, etching or laser drilling until the copper bump 21a is exposed to the surface of the first plastic package body 10a and exposed to the atmosphere, and the outer surface of the first plastic package body 10a near the copper bump 21a is cut to form a plane parallel to the base island 30, see the portion above the dotted line y in fig. 4 and 5.
Regarding step S5: and (6) drilling.
As shown in fig. 6 and 10, fig. 6 is a structural schematic diagram of a drilling state, and fig. 10 is a structural schematic diagram of a package structure for preventing delamination according to a first embodiment of the present invention.
Drilling is performed on one surface of the first plastic package body 10a, which is located on the exposed copper bump 21a, and the drilling is divided into two types, one type is an anti-delamination lock hole c, and the other type is a functional via hole d.
The two types of drilling are performed by adopting laser, mechanical or etching modes, the bottom of the delamination-proof lock hole c extends to the surface of the base island 30, part of the outer surface of the base island 30 is exposed at the bottom of the delamination-proof lock hole c, the central axis of the delamination-proof lock hole c is perpendicular to the surface of the base island 30, during drilling, operation is convenient, production efficiency is improved, but in the actual operation process, the central axis of the delamination-proof lock hole c and the surface of the base island 30 can form an inclined angle rather than a perpendicular state, the delamination-proof effect brought by electroplating at the later stage of the delamination-proof lock hole c with the inclined angle is better, in an effective unit volume, the contact surface between electroplated metal and the first plastic package body 10a can be increased after electroplating of the delamination-proof lock hole c with the inclined angle, and only in specific operation, the inclined delamination-proof lock hole c is drilled more difficult than the perpendicular lock hole c, from this, with technical field personnel can derive very easily, prevent layering lockhole c and just in order to be convenient for realize follow-up electroplating, can pass first plastic-sealed body 10a and the contact of chinampa 30 with the smooth electroplating metal, so prevent layering lockhole c to any shape and size and all be in within the scope of protection of the utility model.
The anti-layering locking holes c can be uniformly formed in the first plastic package body 10a, production and manufacturing are facilitated, even arrangement is not needed in the actual production process, and the position of each anti-layering locking hole c can be properly adjusted according to the difficulty of actual operation or the normal operation of the next procedure.
In this embodiment, the anti-delamination lock hole c is formed in a shape of a plurality of parallel linear holes, and a central axis of the anti-delamination lock hole c is perpendicular to the base island 30.
The bottom of function via hole d extends to the surface of gasket 60, and the surface of gasket 60 exposes in the bottom of function via hole d, function via hole d is in directly over gasket 60, the axis of function via hole d is parallel with the plane that gasket 60 was located, function via hole d is cylindrical, or for the cuboid, or for waist type hole all can, the hole shape listed here, be convenient for implement, and improve production efficiency's structure, of course, for the convenience of the operation of next process, or improve production efficiency, function via hole d also can be the hole of other shapes.
The delamination prevention locking hole c and the functional via hole d can be performed simultaneously.
Regarding step S6: and (4) electroplating.
Referring to fig. 7 and 10, fig. 7 is a schematic structural diagram illustrating an electroplating state, and fig. 10 is a schematic structural diagram illustrating a delamination prevention package structure according to a first embodiment of the present invention.
And performing metal electroplating connection between the copper bump 21a on the chip 21 and the gasket 60 to form a redistribution layer 70, wherein one end of the redistribution layer 70 is fixedly connected with the copper bump 21a of the chip 21, the other end of the redistribution layer extends to the functional via hole d along the outer surface of the first plastic package body 10a and extends along the hole wall of the functional via hole d, and is fixedly connected with the gasket 60 exposed at the bottom of the functional via hole d, the hole wall of the functional via hole d is covered with a layer of electroplating layer to form a metal sunken table 71 with a hat-shaped section, the sunken table 71 protrudes towards the direction of the gasket 60, and the table surface of the sunken table 71 and the surface of the gasket 60 are mutually attached and fixed.
Electroplating is carried out in each anti-layering lockhole c, electroplating is carried out on the inner wall surrounding the anti-layering lockhole c, the connecting piece 51 is formed into a cylindrical shape and is closely attached to and connected with the inner wall of the anti-layering lockhole c, the electroplating is carried out on the bottom of the anti-layering lockhole c while the electroplating is carried out on the inner wall surrounding the anti-layering lockhole c, the formed electroplating layer is fixedly connected with the base island 30, and the electroplating layer and the connecting piece 51 are integrated.
In the actual operation process, the anti-delamination lock hole c can be filled with the electroplated layer to form a strip-shaped connecting piece 51 (the strip-shaped connecting piece 51 is not shown in the figure), so that the electroplating efficiency is improved, and the operation is convenient.
The redistribution layer 70 and the connection 51 can be formed by electroplating at the same time.
Further, electroplating the ear piece 52, and electroplating a circle of electroplating layer on the peripheral edge of one end of the connecting piece 51 far away from the base island 30 while or after electroplating the connecting piece 51 to form the ear piece 52, wherein the ear piece 52 is integrated with the connecting piece 51, and the connecting piece 51 is attached to the outer surface of the first plastic package body 10a and is located on the same horizontal plane with the redistribution layer 70.
In the present embodiment, the ear pieces 52 of two adjacent connecting members 51 do not contact each other.
Regarding step S7: and (5) second packaging.
Referring to fig. 8 in conjunction with fig. 7, fig. 8 is a structural diagram illustrating a second encapsulation state.
The second encapsulation is performed on the basis of the first encapsulation body 10a formed by the first encapsulation to form the encapsulation body 10, the material of the encapsulation body 10 is the same as that used for the first encapsulation body 10a, so that a delamination phenomenon is not easily generated in the later use process, the encapsulation body 10 includes the first encapsulation body 10a, the encapsulation body 10 is integrated with the first encapsulation body 10a (since the encapsulation body 10 is encapsulation performed on the basis of the first encapsulation body 10a, the first encapsulation body 10a is contained in the encapsulation body 10, so that the mark "10 a" is not shown in fig. 8, and only the mark "10" is marked), and the redistribution layer 70, the recessed table 71, the connecting member 51 and the ear piece 52 are all located in the encapsulation body 10.
Regarding step S8: and stripping the carrier plate.
Referring to fig. 9, fig. 9 is a schematic structural diagram of a state after the carrier is peeled off.
The carrier plate b used in step S1 is peeled off, and the peeling process is well-known in the art and is a common process in the technical disclosure, and will not be described in detail herein. After the peeling, the leads 40 are exposed to form outer leads.
The utility model relates to a packaging structure of prevention layering can obtain through above-mentioned production steps.
[ example two ]
A package structure for preventing delamination:
regarding step S1, step S2, step S3, step S4, step S5, step S7, and step S8, the same as in the first embodiment is true, and regarding step S6, the following is specifically made:
referring to fig. 11 and 12 in conjunction with fig. 1 to 10, fig. 11 is a schematic structural diagram of a package structure for preventing delamination in a second embodiment, and fig. 12 is a top view of fig. 11.
Regarding step S6: and (4) electroplating.
In this embodiment, the flow and method of electroplating are the same as those in the first embodiment, except that: the ear pieces 52 on two adjacent connecting pieces 51 are connected with each other to form a whole, so that the electroplating operation is facilitated, and the contact area between the base island 30 and the plastic package body 10 is further increased by increasing the area of the ear pieces 52, so that the probability of layering among the base island, the chip and the plastic package body is greatly reduced.
The utility model relates to a packaging structure of prevention layering can obtain through above-mentioned production steps.
[ EXAMPLE III ]
A package structure for preventing delamination:
regarding step S1, step S2, step S3, step S4, step S7, and step S8, the same as in the first embodiment, regarding step S5 and step S6, the following are concrete:
referring to fig. 13 and 14 in conjunction with fig. 1 to 10, fig. 13 is a schematic structural diagram of a delamination prevention package structure in a third embodiment; fig. 14 is a top view of fig. 13.
Regarding step S5: and (6) drilling.
In this embodiment, the flow and method of drilling are the same as those of the embodiment, but the difference is that during drilling, the shape of the delamination prevention keyhole c is designed into a plurality of arranged pinholes, and the pinholes are all perpendicular to the surface of the base island 30.
Regarding step S6: and (4) electroplating.
In this embodiment, the flow and method of electroplating are the same as those in the first embodiment, except that: in combination with step S5 in the present embodiment, the pinhole-shaped delamination preventing locking hole c is plated, the interior is filled with the plating layer, a rod-shaped connecting member 51 is formed, one end of the connecting member 51 is fixed on the base island 30, the other end is continuously plated, a circular ear piece 52 is formed, the end of the connecting member 51 away from the base island 30 is connected to the center position of the ear piece 51, the rod-shaped connecting member 51 and the circular ear piece 52 are combined with each other, a rivet structure is formed, in other embodiments, the end of the connecting member 51 away from the base island 30 may be connected to any position of the ear piece 51, and two adjacent ear pieces 52 do not contact.
In this embodiment, the combination of the connecting member 51 and the ear member 52 in the rivet structure is uniformly distributed, and in other embodiments, the combination may be distributed in other forms.
The utility model relates to a packaging structure of prevention layering can obtain through above-mentioned production steps.
[ EXAMPLE IV ]
A package structure for preventing delamination:
regarding step S1, step S2, step S3, step S4, step S5, step S7, and step S8, the same as in the first embodiment is true, and regarding step S6, the following is specifically made:
referring to fig. 15 and 16 in conjunction with fig. 1 to 10, fig. 15 is a schematic structural diagram of a delamination prevention package structure in the fourth embodiment; fig. 16 is a top view of fig. 15.
Regarding step S6: and (4) electroplating.
In this embodiment, the flow and method of electroplating are the same as those in the third embodiment, except that: the ear pieces 52 on two adjacent connecting pieces 51 are connected with each other to form a whole, so that the electroplating operation is facilitated, and the contact area between the base island 30 and the plastic package body 10 is further increased by increasing the area of the ear pieces 52, so that the probability of layering among the base island, the chip and the plastic package body is greatly reduced.
The utility model relates to a packaging structure of prevention layering can obtain through above-mentioned production steps.
[ EXAMPLE V ]
A package structure for preventing delamination:
regarding step S1, step S2, step S3, step S4, step S7, and step S8, the same as in the first embodiment, regarding step S5 and step S6, the following are concrete:
please refer to fig. 17 and fig. 18 in combination with fig. 1 to 10, wherein fig. 17 is a schematic structural diagram of a delamination prevention package structure in the fifth embodiment; fig. 18 is a top view of fig. 17.
Regarding step S5: and (6) drilling.
In this embodiment, the first plastic package body 10a is drilled by laser, mechanical or etching to form the wavy anti-delamination locking hole c, the anti-delamination locking hole c in this embodiment has a structure of a continuous wavy surface, and wave crests between adjacent wavy surfaces are connected smoothly, so that the subsequent continuous electroplating operation is facilitated, and the base island 30 below each wave trough on the anti-delamination locking hole c is exposed.
Regarding step S6: and (4) electroplating.
In this embodiment, the flow and method of electroplating are the same as those in the first embodiment, except that: in combination with step S5 in this embodiment, a wavy plating layer is plated on the outer wall of the wavy delamination-preventing lock hole c, and the thickness of the plating layer is uniform.
The electroplated layer in this embodiment is equivalent to the connecting member 51 in the first embodiment, and is located at each trough of the delamination-proof lock hole c, and the electroplated layer is connected and fixed with the base island 30 below the trough of the delamination-proof lock hole c, so that the contact area between the base island 30 and the first plastic package body 10a is increased, the adhesion degree is improved, and the delamination phenomenon is avoided.
In addition, the process flow adopted in this embodiment is high in production efficiency and simple and convenient to operate in steps S5 and S6, and the corrugated plating layer connecting piece 51 is connected to the first plastic package body 10a by relatively opposing a plurality of vertical surfaces in the vertical direction, and is connected to the first plastic package body 10a by a surface equivalent to a whole in the horizontal direction, so that the contact area between the base island 30 and the first plastic package body 10a is maximized, and on this basis, the operation efficiency is simple and convenient.
The utility model relates to a packaging structure of prevention layering can obtain through above-mentioned production steps.
Based on the five package structures obtained in the five embodiments, the most important difference is the package structures with five different structures resulting from the processes of drilling and electroplating, and in other embodiments, at least one of the package structures with the five different structures can be selected on the same package structure to perform a packaging process, so as to form a new package structure.
Compared with the prior art, the utility model, the beneficial effects are as follows:
the utility model provides a prevent packaging structure of layering, adopt the fastener plastic envelope in the plastic envelope, fixed connection between fastener and the base island, thereby increase the area of contact between base island and the plastic envelope, can improve the cohesiveness between the plastic envelope and the base island greatly, and design the fastener into the structure of connecting piece and ear spare, the base island is connected through the connecting piece with the ear spare, the ear spare only blocks the plastic envelope in the plastic envelope, because of the effect of connecting piece, make the base island at chip back or replace between the frame that the base island adopted and the plastic envelope when actually using and lock, effectively prevent the layering between chip and frame or the base island from breaking away from, also prevent the layering between the plastic envelope and the base island or the frame from breaking away from, and in this structure, the fastener can be installed in any place that does not influence other electronic components on the base island, the position can be adjusted in a flexible way, on all encapsulation sizes and the not chip of equidimension that is applicable to the chip package field, because the effect of fastener, increase area of contact between island and the plastic-sealed body, also can improve the heat conduction on the island, thereby make the temperature in the encapsulation body more even, can not produce the phenomenon that temperature deviation is big, also can improve the efficiency that heat energy gived off on the island and the chip of being connected with the island, thereby when reliability test and the practical application in later stage, effectively avoid producing the phenomenon that the layering breaks away from because of high temperature leads to producing between different thermal expansion coefficient's the material, thereby improve the reliability of chip package, promote the performance of chip.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, as any modifications, equivalents, improvements and the like made within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (10)
1. The packaging structure for preventing layering is characterized by comprising a plastic packaging body (10), wherein at least one electronic component is plastically packaged in the plastic packaging body (10), the electronic component is provided with at least one base island (30) and at least one pin (40), the top end of the pin (40) is exposed out of the outer surface of the plastic packaging body (10), the outer surface of the base island (30) is provided with at least one fastener (50), the fastener (50) is fixedly connected with the base island (30), and the fastener (50) is plastically packaged in the plastic packaging body (10).
2. The packaging structure for preventing delamination according to claim 1, wherein the fastening element (50) comprises a connecting element (51) having one end connected to the base island (30), and the other end of the connecting element (51) is molded in the molding compound (10).
3. A delamination prevention package as claimed in claim 2, wherein the fastener (50) further comprises an ear (52) for clamping the plastic package (10), the ear (52) being fixedly connected to the end of the connecting member (51) remote from the base island (30).
4. The packaging structure of claim 1, wherein the electronic component comprises a chip (21), a back surface of the chip (21) is attached to the base island (30), a pad (60) is disposed in the plastic package body (10), the pad (60) is not connected to the base island (30), the lead (40) is disposed on the base island (30) and the pad (60), and the chip (21) and the pad (60) are connected by a redistribution layer (70).
5. A package structure for preventing delamination according to claim 4, wherein said pad (60) is in the same plane and the same thickness as said base island (30), and wherein said pad (60) and said leads (40) on said base island (30) are both on the same side of the plane formed by said pad (60) and said base island (30).
6. The delamination prevention package structure as claimed in any of claims 1 to 5, wherein said leads (40) are outer leads.
7. The anti-delamination package structure according to claim 4, wherein the redistribution layer (70) is parallel to the base island (30), a recessed mesa (71) having a hat-shaped cross section is disposed at an end of the redistribution layer (70) connected to the pad (60), the recessed mesa (71) protrudes toward the pad (60), and a mesa of the recessed mesa (71) and a surface of the pad (60) are attached to each other and fixed.
8. The package structure of claim 7, wherein the base island (30) and the pad (60) are made of copper.
9. A package structure for preventing delamination according to claim 3, wherein said connecting member (51) and said ear member (52) are made of a metal capable of being plated.
10. A delamination prevention package as claimed in claim 4, wherein the chip (21) and the base island (30) are connected by a metal transition layer, and the metal transition layer comprises at least one of TiNiAg, TiAu or TiCu.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921693748.9U CN210272320U (en) | 2019-10-11 | 2019-10-11 | Packaging structure for preventing layering |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201921693748.9U CN210272320U (en) | 2019-10-11 | 2019-10-11 | Packaging structure for preventing layering |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN210272320U true CN210272320U (en) | 2020-04-07 |
Family
ID=70020116
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201921693748.9U Active CN210272320U (en) | 2019-10-11 | 2019-10-11 | Packaging structure for preventing layering |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN210272320U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110556343A (en) * | 2019-10-11 | 2019-12-10 | 合肥矽迈微电子科技有限公司 | Packaging structure and packaging process for preventing layering |
-
2019
- 2019-10-11 CN CN201921693748.9U patent/CN210272320U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110556343A (en) * | 2019-10-11 | 2019-12-10 | 合肥矽迈微电子科技有限公司 | Packaging structure and packaging process for preventing layering |
| CN110556343B (en) * | 2019-10-11 | 2024-04-12 | 合肥矽迈微电子科技有限公司 | Packaging structure and packaging process for preventing layering |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101937948B1 (en) | Integrated circuit packaging system with stacked lead and method of manufacture thereof | |
| CN110556343B (en) | Packaging structure and packaging process for preventing layering | |
| JP2004048024A (en) | Semiconductor integrated circuit device and its manufacturing method | |
| JPH11260985A (en) | Lead frame, resin-sealed semiconductor device and its manufacture | |
| TW201532235A (en) | Fine pitch BVA using reconstituted wafer with area array accessible for testing | |
| JP3837215B2 (en) | Individual semiconductor device and manufacturing method thereof | |
| CN102569101A (en) | Outer pin-free packaging structure and manufacturing method thereof | |
| CN110473795B (en) | Layered isolation packaging structure and process for large-size chip | |
| CN210272320U (en) | Packaging structure for preventing layering | |
| US20040084757A1 (en) | Micro leadframe package having oblique etching | |
| CN210156364U (en) | Layered isolation packaging structure of large-size chip | |
| CN102751204B (en) | Fanout type wafer level chip packaging method | |
| US10049966B2 (en) | Semiconductor device and corresponding method | |
| JP3250900B2 (en) | Semiconductor device, method of manufacturing the same, and lead frame | |
| CN112992839B (en) | Lead frame for chip packaging and preparation method | |
| CN109037082A (en) | Encapsulating structure and forming method thereof | |
| CN110581079B (en) | Fan-out type chip packaging method and fan-out type chip packaging body | |
| WO2016107298A1 (en) | Molding packaged mini mobile phone intelligent card, and packing method | |
| CN210182335U (en) | Five-sided metal encapsulation packaging structure | |
| CN209374429U (en) | Packaging body | |
| JP2002033345A (en) | Method for manufacturing resin-sealed semiconductor device | |
| CN108962772A (en) | Encapsulating structure and forming method thereof | |
| CN114823550B (en) | Chip packaging structure and packaging method suitable for batch production | |
| CN108962766A (en) | Encapsulating structure and forming method thereof | |
| CN215644487U (en) | Sensor packaging structure with logic chip packaged in advance |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Assignee: Anhui Xingtai Financial Leasing Co.,Ltd. Assignor: Hefei Silicon Microelectronics Technology Co.,Ltd. Contract record no.: X2023980036895 Denomination of utility model: A packaging structure for preventing layering Granted publication date: 20200407 License type: Exclusive License Record date: 20230627 |
|
| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A packaging structure for preventing layering Effective date of registration: 20230628 Granted publication date: 20200407 Pledgee: Anhui Xingtai Financial Leasing Co.,Ltd. Pledgor: Hefei Silicon Microelectronics Technology Co.,Ltd. Registration number: Y2023980046373 |