CN215007527U

CN215007527U - Upper and lower memory module that divides

Info

Publication number: CN215007527U
Application number: CN202121171291.2U
Authority: CN
Inventors: 袁嘉玲
Original assignee: Xiamen Atom Tong Electronic Technology Co ltd
Current assignee: Xiamen Atom Tong Electronic Technology Co ltd
Priority date: 2021-05-28
Filing date: 2021-05-28
Publication date: 2021-12-03
Anticipated expiration: 2031-05-28

Abstract

The utility model discloses a divide position memory module from top to bottom, it includes: the device comprises a memory unit, a variable power supply module, a driving module and a circuit board, wherein the memory unit, the variable power supply module and the driving module are all connected to the circuit board; the memory unit comprises at least four memory chip units, at least one memory chip unit comprises a first memory chip and a second memory chip, the first memory chip and the second memory chip are both damaged memory chips, and the damaged memory chips are the damaged memory chips on the upper half part or the damaged memory chips on the lower half part in the chips; the first memory chip and the second memory chip are both provided with BG0 terminals and BG1 terminals, the BG0 terminal of the first memory chip is connected with the BG0 terminal of the second memory chip, the output end of the variable power supply module is connected with the input end of the driving module, and the output end of the driving module is connected with the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip in parallel. Through the splicing circuit technology, the chip is fully utilized, and the cost is reduced.

Description

Upper and lower memory module that divides

Technical Field

The utility model relates to a memory chip module technical field, concretely relates to divide position memory module from top to bottom.

Background

With the rapid development of electronic products, many electronic products need to be applied to a memory chip to store data information. The memory module is reasonably arranged on the PCB so as to achieve the function of storing data of the memory module. At present, in the production test process of the memory module, a part of bad chips can inevitably occur, the bad chips can have a bad defect address range, and the bad chips can not realize all functions due to certain defects, and are often discarded, so that the waste of the chips is caused.

Therefore, in view of the above problems, the conventional chip module needs to be further improved to reuse the defective memory chip.

SUMMERY OF THE UTILITY MODEL

The purpose of the utility model is to overcome the waste problem of bad chips, to the memory chip of bad defect address range appearing in the normal test process, through the concatenation circuit technology of the memory unit, after recombining the bad memory chip, rationally arrange on the circuit board, can obtain the memory module after the concatenation; specifically, the memory chip unit with the damaged memory chip is adopted and connected with the driving module, the driving module is connected with the variable power supply module, the output voltage is changed through the variable power supply module, the output voltage is transmitted to the driving module and then transmitted to the memory chip unit, and the memory chips in the memory chip unit can be spliced; the BG0 terminals and the BG1 terminals of two memory chips with the same damage are connected in common, the BG1 terminals are connected with the output end of the driving module, the input end of the driving module is connected with the output end of the variable power supply module, splicing of the memory chips with the same damage can be effectively realized, and bad memory chips are reused.

The technical scheme of the utility model is specifically as follows:

a split-bit memory module, comprising: the device comprises a memory unit, a variable power supply module, a driving module and a circuit board, wherein the memory unit, the variable power supply module and the driving module are all connected to the circuit board;

the memory unit comprises at least four memory chip units, at least one memory chip unit is formed by combining a first memory chip and a second memory chip, the first memory chip and the second memory chip are the same damaged memory chips, and the same damaged memory chips are the memory chips damaged at the upper half part or the memory chips damaged at the lower half part in the chips;

the first memory chip and the second memory chip are provided with BG0 terminals and BG1 terminals, the BG0 terminal of the first memory chip is connected with the BG0 terminal of the second memory chip, the output end of the variable power supply module is connected with the input end of the driving module, and the output end of the driving module is connected with the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip in parallel.

Further, variable power module is the power that can provide the VDD voltage, the VDD voltage is the inside operating voltage of device, drive module is resistance R1, first memory chip and second memory chip are the memory chip of the inside first damage of chip, resistance R1's one end parallel connection the BG1 terminal of first memory chip with the BG1 terminal of second memory chip, the output of VDD's power is connected to resistance R1's the other end.

Further, the variable power module is a power supply capable of providing a VSS voltage, the VSS voltage is a voltage of a circuit common ground, the driving module is a resistor R2, the first memory chip and the second memory chip are both memory chips damaged at the lower half part inside the chips, one end of the resistor R2 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, and the other end of the resistor R2 is connected with an output end of the VSS power supply.

Further, the VDD voltage is a positive voltage.

Further, in the memory unit, all the memory chip units are formed by combining a first memory chip and a second memory chip.

Further, the first memory chip and the second memory chip are both DDR4 memory chips.

Further, the number of the memory chip units is 4 or 8.

Advantageous effects

The utility model discloses a concatenation circuit technology of memory cell, after recombining bad memory chip, rationally arrange on the circuit board, can obtain the memory module after the concatenation; specifically, the memory chip unit with the damaged memory chip is connected with the driving module, the driving module is connected with the variable power module, the output voltage is changed through the variable power module, the output voltage is transmitted to the driving module and then transmitted to the memory chip unit, and the memory chips in the memory chip unit can be spliced; the BG0 terminals and the BG1 terminals of two memory chips with the same damage are connected in common, the BG1 terminals are connected with the output end of the driving module, the input end of the driving module is connected with the output end of the variable power supply module, splicing of the memory chips with the same damage can be effectively realized, and bad chips are reused.

In a specific implementation mode, a power supply VDD and a resistor R1 are adopted, one end of a resistor R1 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, so that two memory chips (memory chips with good lower half parts and bad upper half parts) with the same damage can be effectively driven by the same power supply to work, memory modules with unchanged memory capacity, speed, functions and the like can be effectively reduced by half, the chips are fully utilized, and the cost is reduced.

In another specific embodiment, a power supply VSS and a resistor R2 are used as a matching circuit, and one end of a resistor R2 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, so that two memory chips with the same damage (memory chips with good upper half and bad lower half) can work under the same power supply drive effectively, memory modules with unchanged memory capacity, speed, functions and the like can be reduced by half effectively, the chips are fully utilized, and the cost is reduced.

Drawings

Fig. 1 is a schematic structural view of an upper and lower split-level memory module according to the present invention.

Fig. 2 is a schematic diagram of the structure of the split joint of the memory chip units of the upper and lower split-level memory module of the present invention.

Fig. 3 is a schematic diagram of the structure of the memory chip unit splicing of the upper half bad and the lower half good of the upper and lower split memory module of the present invention.

Fig. 4 is a schematic diagram of the structure of the split memory module according to the present invention, in which the memory chip units are spliced in the first half and the second half.

Fig. 5 is a block diagram illustrating the chip internal selection of the memory module according to the present invention.

Reference numerals: 1. a circuit board; 2. a memory unit; 3. a drive module; 4. a variable power supply module; 21. a first memory chip; 22. and a second memory chip.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.

Referring to fig. 1, the utility model provides a pair of divide position memory module from top to bottom, divide position memory module from top to bottom includes: the power supply comprises a memory unit 2, a variable power supply module 4, a driving module 3 and a circuit board 1, wherein the memory unit 2, the variable power supply module 4 and the driving module 3 are all connected to the circuit board 1;

the memory unit 2 comprises at least four memory chip units, at least one memory chip unit is formed by combining a first memory chip 21 and a second memory chip 22, the first memory chip 21 and the second memory chip 22 are the same damaged memory chips, and the same damaged memory chips are the memory chips damaged at the upper half part or the memory chips damaged at the lower half part in the chips;

referring to fig. 2, the first memory chip 21 and the second memory chip 22 are both provided with a BG0 terminal and a BG1 terminal, the BG0 terminal of the first memory chip 21 is connected to the BG0 terminal of the second memory chip 22, the output end of the variable power supply module 4 is connected to the input end of the driving module 3, and the output end of the driving module 3 is connected in parallel to the BG1 terminal of the first memory chip 21 and the BG1 terminal of the second memory chip 22.

In an embodiment, referring to fig. 3, based on fig. 2, the variable power module 4 is a power supply capable of providing VDD voltage, the VDD voltage is a working voltage inside the device, the driving module 3 is a resistor R1, the first memory chip 21 and the second memory chip 22 are both memory chips with upper half damaged inside the chip, one end of the resistor R1 is connected in parallel to the BG1 terminal of the first memory chip 21 and the BG1 terminal of the second memory chip 22, and the other end of the resistor R1 is connected to an output end of the power supply of VDD.

In a second embodiment, referring to fig. 4, based on fig. 2, the variable power module 4 is a power supply capable of providing a VSS voltage, the VSS voltage is a voltage of a circuit common ground, the driving module 3 is a resistor R2, the first memory chip 21 and the second memory chip 22 are both memory chips damaged at the lower half portions inside the chips, one end of the resistor R2 is connected in parallel with a BG1 terminal of the first memory chip 21 and a BG1 terminal of the second memory chip 22, and the other end of the resistor R2 is connected to an output end of the VSS power supply.

In a third embodiment, based on the first or second embodiment, in the memory unit 2, all memory chip units are formed by combining the first memory chip 21 and the second memory chip 22.

Wherein the VDD voltage is a positive voltage. The first memory chip 21 and the second memory chip 22 are DDR4 memory chips.

Fig. 5 is a block diagram illustrating an internal selection of a memory module in a split-bit manner under a good condition, where, as shown in fig. 5, a BG 1-0 region in the memory chip is set as an upper half portion, and a BG 1-1 region in the memory chip is set as a lower half portion.

The utility model discloses implement the principle: by adopting the variable power module and the driving module and connecting the damaged memory chips in a specific mode, 8 similar bad chips can be spliced into a memory chip module with 4 capacities reduced by half and complete functions; 16 similar bad chips can be spliced into 8 memory chip modules with capacity halved and complete functions, and the like.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. The upper and lower split-bit memory module is characterized by comprising: the device comprises a memory unit, a variable power supply module, a driving module and a circuit board, wherein the memory unit, the variable power supply module and the driving module are all connected to the circuit board;

2. The memory module of claim 1, wherein the variable power module is a power supply capable of providing a VDD voltage, the VDD voltage is an operating voltage inside a device, the driving module is a resistor R1, the first and second memory chips are both damaged memory chips on the upper half inside the chips, one end of the resistor R1 is connected in parallel to the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip, and the other end of the resistor R1 is connected to an output terminal of the VDD power supply.

3. The upper and lower bit-splitting memory module as claimed in claim 1, wherein the variable power module is a power supply capable of providing VSS voltage, the VSS voltage is a voltage of a circuit common ground, the driving module is a resistor R2, the first memory chip and the second memory chip are both memory chips with damaged lower half portions inside the chips, one end of the resistor R2 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, and the other end of the resistor R2 is connected with an output end of the VSS power supply.

4. The split-bit memory module as claimed in claim 2, wherein the VDD voltage is a positive voltage.

5. The memory module of claim 1, wherein all of the memory chips are formed by a combination of a first memory chip and a second memory chip.

6. The memory module of claim 5, wherein the number of the memory chip units is 4 or 8.

7. The split-bit memory module as claimed in claim 1, wherein the first and second memory chips are both DDR4 memory chips.