CN215007529U

CN215007529U - Twin-crystal-to-single-crystal memory module

Info

Publication number: CN215007529U
Application number: CN202121171487.1U
Authority: CN
Inventors: 孔凡平
Original assignee: Xiamen Atom Tong Electronic Technology Co ltd
Current assignee: Xiamen Atom Tong Electronic Technology Co ltd
Priority date: 2021-05-28
Filing date: 2021-05-28
Publication date: 2021-12-03
Anticipated expiration: 2031-05-28

Abstract

The utility model relates to a memory chip module technical field discloses a bimorph changes single crystal memory module, include: the memory module comprises a memory chip, a DIMM module, a driving module and a circuit board, wherein the memory chip, the DIMM module and the driving module are all connected to the circuit board; the memory chip is a memory chip with a bad upper wafer or a memory chip with a bad lower wafer in the chip; the input end of the DIMM module is connected with the output end of the CPU module, the RCKE0, RCKE1, RODT0, RODT1, RS0_ N, RS1_ N, VDD and VSS terminals of the DIMM module are connected with the eight input ends of the driving module, and the eight output ends of the driving module are connected with CKE0, CKE1, ODT0, ODT1, CS0, CS1, VDD and VSS terminals of the memory chip. The memory module realizes that the twin crystal of the memory chip is changed into the single crystal, and the bad memory chip is reused.

Description

Twin-crystal-to-single-crystal memory module

Technical Field

The utility model relates to a memory chip module technical field, concretely relates to bimorph changes single crystal memory module.

Background

With the rapid development of electronic products, many electronic products need to be applied to a memory chip to store data information. The memory module is reasonably arranged on the circuit board so as to achieve the data storage function of the memory module. At present, in a normal memory module, a good memory chip is generally reasonably arranged on a circuit board, the memory chip generally includes an upper wafer and a lower wafer inside the chip, an address CKE0 terminal, an ODT0 terminal, a CS0 terminal of the memory chip are disposed on the upper wafer and a CKE1 terminal, an ODT1 terminal, a CS1 terminal are disposed on the lower wafer, as shown in fig. 2, the CUP module outputs electrical signals required by the CKE0 terminal, the CKE1 terminal, the ODT0 terminal, the ODT1 terminal, the CS0 terminal, the CS1 terminal, the VDD terminal, and the VSS terminal of the memory chip to an RCKE0 terminal, an RCKE1 terminal, a RODT0 terminal, a RODT1 terminal, an RS0_ N terminal, an RS1_ N terminal, a VDD terminal, and a VSS terminal of the DIMM module, the CKE0 terminal of the DIMM module is connected with an RB 0 terminal of the DIMM chip through a resistor 0, the RCKE0 terminal of the DIMM module is connected with the RCKE0 terminal of the dram module through the resistor 0, the DIMM module 0, and the RCKE0 is connected with the RCKE0 through the resistor 0 of the DIMM module 0, the RODT1 terminal of the DIMM module is connected with the ODT1 terminal of the memory chip through a resistor RB4, the RS0_ N terminal of the DIMM module is connected with the CS0 terminal of the memory chip through a resistor RC1, the RS1_ N terminal of the DIMM module is connected with the CS1 terminal of the memory chip through a resistor RC4, and the VDD terminal and the VSS terminal of the DIMM module are respectively connected with the VDD terminal and the VSS terminal of the memory chip; however, during the production test of the memory module, some bad chips are inevitably generated. For example, memory chips with defective address ranges may occur, and these memory chips with defective address ranges may not implement all functions and are often discarded, resulting in waste of chips.

Therefore, in view of the above problems, the conventional chip module needs to be further improved to reuse the memory chip with the defective address range.

SUMMERY OF THE UTILITY MODEL

The utility model aims at overcoming the problem of memory chip waste in the bad defect address range, and reasonably arranging the memory chip in the bad defect address range in the normal test process on a circuit board after recombining the bad memory chip by the circuit technology of changing the bicrystal of the memory chip into the monocrystal, so as to obtain a memory module after changing the bicrystal into the monocrystal; specifically, a memory chip with bad performance is adopted and connected with a driving module, the driving module is connected with a DIMM module, output voltage change is carried out through the DIMM module, the output voltage change is transmitted to the driving module and then transmitted to the memory chip, and double-crystal-to-single-crystal conversion of the memory chip can be realized; the address CKE0 terminal, CKE1 terminal, ODT0 terminal, ODT1 terminal, CS0 terminal, CS1 terminal, VDD terminal and VSS terminal of the memory chip are connected with the output end of the driving module, the RCKE0 terminal, RCKE1 terminal, RODT0 terminal, RODT1 terminal, RS0_ N terminal, RS1_ N terminal, VDD terminal and VSS terminal of the DIMM module are connected with the input end of the driving module, wherein the CS0 terminal or CS1 terminal of the memory chip is used for receiving high-level voltage from the output end of the driving module, double crystal changing of the memory chip can be effectively realized, and the defective memory chip can be reused.

The technical scheme of the utility model is specifically as follows:

a twin crystal-to-single crystal memory module, comprising: the memory module comprises a memory chip, a DIMM module, a driving module and a circuit board, wherein the memory chip, the DIMM module and the driving module are all connected to the circuit board;

the number of the memory chips is 8n or 9n, n is a positive integer, and the memory chips are memory chips with poor upper-layer wafers and good lower-layer wafers inside the chips or memory chips with poor lower-layer wafers and good upper-layer wafers inside the chips;

the memory chip is provided with an address CKE0 terminal, a CKE1 terminal, an ODT0 terminal, an ODT1 terminal, a CS0 terminal, a CS1 terminal, a VDD terminal and a VSS terminal, the DIMM module is provided with a VDD terminal, a VSS terminal, an RCKE0 terminal, a RODT0 terminal, an RS0_ N terminal and an RS0_ N terminal, the address CKE0 terminal, the ODT0 terminal, the CS0 terminal and the CS0 terminal of the memory chip correspond to the RCKE0 terminal, the RODT0 terminal, the RS0_ N terminal and the RS0_ N terminal of the DIMM module respectively, the input end of the DIMM module is connected with the output end of the CPU module, the RCKE0 terminal, the RODT0 terminal, the VSS 0 terminal, the RS0 terminal, the RODT0 terminal, the input end of the RCKE0 terminal of the RODT0 terminal and the eight input end of the DIMM module are connected with the eight internal driving module, the eight driving module, and the eight internal driving module, The memory chip comprises a CKE1 terminal, an ODT0 terminal, an ODT1 terminal, a CS0 terminal, a CS1 terminal, a VDD terminal and a VSS terminal, wherein the CS0 terminal or the CS1 terminal of the memory chip is used for receiving a high-level voltage required by a digital circuit from an output end of the driving module, the VSS terminal is provided with a VSS voltage, and the VDD terminal is provided with a VDD voltage.

Further, the memory chip is a memory chip with a poor lower wafer and a good upper wafer in the chip, the address CKE0 terminal, the ODT0 terminal, and the CS0 terminal of the memory chip are disposed on the upper wafer, the CKE1 terminal, the ODT1 terminal, and the CS1 terminal of the memory chip are disposed on the lower wafer, the driving module includes a resistor RA1, a resistor RA5, a resistor RB1, a resistor RB5, a resistor RC1, a resistor RC5, and two wires, the RCKE0 terminal of the DIMM module is connected to the input terminal of the resistor RA1, the output terminal of the resistor RA1 is connected to the address CKE0 terminal of the memory chip, the VSS terminal of the DIMM module is connected to the input terminal of the resistor RA5, the output terminal of the resistor RA5 is connected to the address CKE1 terminal of the memory chip, the DIMM dt0 terminal of the DIMM module is connected to the input terminal of the resistor RB1, the output terminal of the resistor RB1 is connected to the address terminal of the internal chip 0, and the ODT 5 terminal of the DIMM module is connected to the input terminal of the resistor r 38725, the output end of the resistor RB5 is connected with an address ODT1 terminal of the memory chip, the RS0_ N terminal of the DIMM module is connected with the input end of the resistor RC1, the output end of the resistor RC1 is connected with an address CS0 terminal of the memory chip, the VDD terminal of the DIMM module is connected with the input end of the resistor RC5, the output end of the resistor RC5 is connected with the address CS1 terminal of the memory chip, the VSS terminal of the DIMM module is connected with the VSS terminal of the memory chip through one conducting wire of the driving module, and the VDD terminal of the DIMM module is connected with the VDD terminal of the memory chip through the other conducting wire of the driving module.

Further, the memory chip is a memory chip having a bad upper wafer and a good lower wafer in the chip, the address CKE0 terminal, the ODT0 terminal, and the CS0 terminal of the memory chip are disposed on the upper wafer, the CKE1 terminal, the ODT1 terminal, and the CS1 terminal of the memory chip are disposed on the lower wafer, the driving module includes a resistor RA2, a resistor RA3, a resistor RB2, a resistor RB3, a resistor RC2, a resistor RC3, and two wires, the RCKE0 terminal of the DIMM module is connected to the input terminal of the resistor RA3, the output terminal of the resistor RA3 is connected to the address CKE1 terminal of the memory chip, the VSS terminal of the DIMM module is connected to the input terminal of the resistor RA2, the output terminal of the resistor RA2 is connected to the address CKE0 terminal of the memory chip, the DIMM dt0 terminal of the DIMM module is connected to the input terminal of the resistor RB3, the address RB3 is connected to the address RB terminal of the internal chip, and the ODT1 of the resistor RB2 is connected to the input terminal of the resistor RB2, the output end of the resistor RB2 is connected with an address ODT0 terminal of the memory chip, the RS0_ N terminal of the DIMM module is connected with the input end of the resistor RC3, the output end of the resistor RC3 is connected with an address CS1 terminal of the memory chip, the VDD terminal of the DIMM module is connected with the input end of the resistor RC2, the output end of the resistor RC2 is connected with the address CS0 terminal of the memory chip, the VSS terminal of the DIMM module is connected with the VSS terminal of the memory chip through one conducting wire of the driving module, and the VDD terminal of the DIMM module is connected with the VDD terminal of the memory chip through the other conducting wire of the driving module.

Further, the VDD voltage is a positive voltage.

Further, the memory chip is a DDR4 memory chip.

Further, the number of the memory chips is eight or nine or sixteen or eighteen.

Further, the RCKE0 terminal of the DIMM module is an electrical signal required for being able to transmit to the address CKE0 terminal of the memory chip.

Further, the RCKE1 terminal of the DIMM module is an electrical signal required for being able to transmit to the address CKE1 terminal of the memory chip.

Further, the RODT0 terminal of the DIMM module is an electrical signal required for being able to transmit to the address ODT0 terminal of the memory chip.

Further, the RODT1 terminal of the DIMM module is an electrical signal required for being able to transmit to the address ODT1 terminal of the memory chip.

Further, the RS0_ N terminal of the DIMM module is an electrical signal required for being able to transmit to the address CS0 terminal of the memory chip.

Further, the RS1_ N terminal of the DIMM module is an electrical signal required for being able to transmit to the address CS1 terminal of the memory chip.

Further, the VDD terminal may transmit a VDD voltage, which is an operating voltage inside the device.

Further, the VSS terminal may transmit a VSS voltage, which is a circuit common ground voltage.

Advantageous effects

The utility model changes the memory chip of bad defect address range in the normal test process into the single crystal through the twin crystal of the memory chip, after the bad memory chip is recombined, the memory chip is reasonably arranged on the circuit board, and the memory module group after the twin crystal is changed into the single crystal can be obtained; specifically, a memory chip with bad performance is adopted and connected with a driving module, the driving module is connected with a DIMM module, output voltage change is carried out through the DIMM module, the output voltage change is transmitted to the driving module and then transmitted to the memory chip, and double-crystal-to-single-crystal conversion of the memory chip can be realized; the address CKE0 terminal, CKE1 terminal, ODT0 terminal, ODT1 terminal, CS0 terminal, CS1 terminal, VDD terminal and VSS terminal of the memory chip are connected with the output end of the driving module, the RCKE0 terminal, RCKE1 terminal, RODT0 terminal, RODT1 terminal, RS0_ N terminal, RS1_ N terminal, VDD terminal and VSS terminal of the DIMM module are connected with the input end of the driving module, wherein the CS0 terminal or CS1 terminal of the memory chip is used for receiving high-level voltage from the output end of the driving module, double crystal changing of the memory chip can be effectively realized, and the defective memory chip can be reused.

In a specific embodiment, a VDD terminal is connected with a resistor RC5, a VSS terminal is connected with a matching circuit of a resistor RB5 and a resistor RA5, a resistor RC5 provides a high level for a CS1 terminal of a memory chip, a resistor RB5 and a resistor RA5 provide a low level for an ODT1 terminal and a CKE1 terminal of the memory chip, and output terminals of a resistor RA1, a resistor RB1 and a resistor RC1 are connected with an address CKE0 terminal, an ODT0 terminal and an S0_ N terminal of the memory chip, so that a twin crystal of a defective memory chip (a memory chip with a good upper wafer and a memory chip with a poor lower wafer) can be effectively changed into a single crystal, a memory module with reduced memory capacity by half, unchanged speed and function and the like can be effectively realized, the chips are fully utilized, and the cost is reduced.

In another specific embodiment, a VDD terminal is connected with a resistor RC2, a VSS terminal is connected with a matching circuit of a resistor RB2 and a resistor RA2, a resistor RC2 provides a high level for a CS0 terminal of a memory chip, a resistor RB2 and a resistor RA2 provide a low level for an ODT0 terminal and a CKE0 terminal of the memory chip, and output terminals of a resistor RA3, a resistor RB3 and a resistor RC3 are connected with an address CKE0 terminal, an ODT0 terminal and an S0_ N terminal of the memory chip, so that a bicrystal-to-single crystal conversion of a defective memory chip (a memory chip with a defective upper wafer and a good lower wafer) can be effectively realized, a memory module with reduced memory capacity by half, unchanged speed and functions and the like can be effectively realized, the chips are fully utilized, and the cost is reduced.

Drawings

Fig. 1 is a schematic structural view of a single crystal memory module modified from a twin crystal memory module according to the present invention.

Fig. 2 is a schematic diagram of the memory module with good memory chips according to the present invention.

Fig. 3 is a schematic structural view of a bad memory chip of the single crystal memory module with a twin crystal changing from a single crystal according to the present invention.

Fig. 4 is a schematic structural diagram of a memory chip with good upper-layer wafer and bad lower-layer wafer of the single-crystal memory module according to the present invention.

Fig. 5 is a schematic structural diagram of a memory chip with good lower layer wafer and bad upper layer wafer of the single crystal memory module according to the present invention.

Fig. 6 is a block diagram of the internal selection of the memory chip of the single crystal memory module according to the present invention.

Reference numerals: 1. a circuit board; 2. a memory chip; 3. a drive module; 4. a DIMM module; 21. a first memory chip; 22. an Nth memory chip; 51. and a CPU module.

Detailed Description

The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

Referring to fig. 1, the utility model provides a pair of single crystal memory module is changed to bimorph, the single crystal memory module is changed to bimorph includes: the memory module comprises a memory chip 2, a DIMM module 4, a driving module 3 and a circuit board 1, wherein the memory chip 2, the DIMM module 4 and the driving module 3 are all connected to the circuit board 1.

The number of the memory chips 2 is 8n or 9n, n is a positive integer, and the memory chips 2 are memory chips with poor upper-layer wafers and good lower-layer wafers inside the chips, or memory chips with poor lower-layer wafers and good upper-layer wafers inside the chips.

Referring to fig. 3, the memory chip 2 is provided with an address CKE0 terminal, a CKE1 terminal, an ODT0 terminal, an ODT1 terminal, a CS0 terminal, a CS1 terminal, a VDD terminal, and a VSS terminal, the DIMM module 4 is provided with a VDD terminal, a VSS terminal, an RCKE0 terminal, a RODT0 terminal, an RS0_ N terminal, and an RS0_ N terminal, the address CKE0 terminal, the ODT0 terminal, the CS0 terminal, and the CS0 terminal of the memory chip 2 correspond to the RCKE0 terminal, the RODT0 terminal, the RS0_ N terminal, and the RS0_ N terminal of the DIMM module 4, the input terminal of the DIMM module 4 is connected to the output terminal of the CPU module, the RCKE0 terminal, the rcvss 0 terminal, the rovss 0 terminal, the RODT0 terminal, the RS0 terminal, the RODT0 terminal of the input terminal of the DIMM module 4 is connected to the eight input terminal of the CPU module 363, and the eight input terminal of the memory chip drive module 0, and the eight input terminal of the RCKE0 are connected to the input terminal of the CPU module 4, and the RCKE0, the eight drive module 0, and the eight drive module 0 terminal of the rdt 0, and the eight drive module, The memory chip 2 includes a CKE1 terminal, an ODT0 terminal, an ODT1 terminal, a CS0 terminal, a CS1 terminal, a VDD terminal, and a VSS terminal, and the CS0 terminal or the CS1 terminal of the memory chip 2 is used to receive a high-level voltage required in a digital circuit from an output terminal of the driving module 3, the VSS terminal has a VSS voltage, and the VDD terminal has a VDD voltage. The memory chips 2 include first to nth memory chips 21 to 22, where N is 8N or 9N, and N is a positive integer (only the first and last memory chips are shown in the figure).

In an embodiment, referring to fig. 4, based on fig. 3, the memory chip 2 is a memory chip having a poor lower wafer and a good upper wafer inside the chip, the address CKE0 terminal, the ODT0 terminal, and the CS0 terminal of the memory chip 2 are disposed on the upper wafer, and the CKE1 terminal, the ODT1 terminal, and the CS1 terminal of the memory chip 2 are disposed on the lower wafer, the driving module 3 includes a resistor RA1, a resistor RA5, a resistor RB1, a resistor RB5, a resistor RC1, a resistor RC5, and two wires, the RCKE0 terminal of the DIMM module 4 is connected to the input terminal of the resistor RA1, the output terminal of the resistor RA1 is connected to the address CKE0 terminal of the memory chip 2, the VSS terminal of the DIMM module 4 is connected to the input terminal of the resistor RA5, the output terminal of the resistor RA5 is connected to the address CKE1 terminal of the memory chip 2, the RODT0 terminal of the DIMM module 4 is connected to the input terminal of the resistor RB 0 terminal, the resistor RA 0 terminal of the resistor 0 is connected to the address terminal of the memory chip 1, the VSS terminal of the DIMM module 4 is connected with the input end of the resistor RB5, the output end of the resistor RB5 is connected with the address ODT1 terminal of the memory chip 2, the RS0_ N terminal of the DIMM module 4 is connected with the input end of the resistor RC1, the output end of the resistor RC1 is connected with the address CS0 terminal of the memory chip 2, the VDD terminal of the DIMM module 4 is connected with the input end of the resistor RC5, the output end of the resistor RC5 is connected with the address CS1 terminal of the memory chip 2, the VSS terminal of the DIMM module 4 is connected with the VSS terminal of the memory chip 2 through one lead of the driving module 3, and the VDD terminal of the DIMM module 4 is connected with the VDD terminal of the memory chip 2 through the other lead of the driving module 3.

In a second embodiment, referring to fig. 5, based on the illustration in fig. 3, the memory chip 2 is a memory chip with a bad upper wafer and a good lower wafer inside the chip, the address CKE0 terminal, the ODT0 terminal, and the CS0 terminal of the memory chip 2 are disposed on the upper wafer, the CKE1 terminal, the ODT1 terminal, and the CS1 terminal are disposed on the lower wafer, the driving module 3 includes a resistor RA2, a resistor RA3, a resistor RB2, a resistor RB3, a resistor RC2, a resistor RC3, and two wires, the RCKE0 terminal of the DIMM module 4 is connected to the input terminal of the resistor RA3, the output terminal of the resistor RA3 is connected to the address CKE1 terminal of the memory chip 2, the VSS terminal of the DIMM module 4 is connected to the input terminal of the resistor RA2, the output terminal of the resistor RA2 is connected to the address CKE0 terminal of the memory chip 2, the RODT0 terminal of the DIMM module 4 is connected to the input terminal of the resistor RB 0 terminal, the resistor RA 0 terminal of the DIMM 3 is connected to the address terminal 1, the VSS terminal of the DIMM module 4 is connected with the input end of the resistor RB2, the output end of the resistor RB2 is connected with the address ODT0 terminal of the memory chip 2, the RS0_ N terminal of the DIMM module 4 is connected with the input end of the resistor RC3, the output end of the resistor RC3 is connected with the address CS1 terminal of the memory chip 2, the VDD terminal of the DIMM module 4 is connected with the input end of the resistor RC2, the output end of the resistor RC2 is connected with the address CS0 terminal of the memory chip 2, the VSS terminal of the DIMM module 4 is connected with the VSS terminal of the memory chip 2 through one lead of the driving module 3, and the VDD terminal of the DIMM module 4 is connected with the VDD terminal of the memory chip 2 through the other lead of the driving module 3.

Wherein the VDD voltage is a positive voltage. The memory chip is a DDR4 memory chip. The first memory chip 21 to the nth memory chip 2N are all memory chips in a bad defect address range occurring in a normal test process.

Fig. 6 is a block diagram illustrating an internal selection of a memory chip of the twin-crystal to single-crystal memory module, and referring to fig. 6, an upper wafer region in the memory chip is set as an upper wafer portion, and a lower wafer region in the memory chip is set as a lower wafer portion.

The utility model discloses implement the principle: the variable power module and the driving module are adopted, bad memory chips are connected in a specific mode, the capacity of the bad memory chips is halved, and the speed, the function and the like are not changed; a memory module with eight memory chips, or a memory module with nine memory chips, or a memory module with sixteen memory chips, or a memory module with eighteen memory chips, etc. may be implemented.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A twin crystal-to-single crystal memory module, comprising: the memory module comprises a memory chip, a DIMM module, a driving module and a circuit board, wherein the memory chip, the DIMM module and the driving module are all connected to the circuit board;

2. The twinned crystal-changed memory module as claimed in claim 1, wherein the memory chip is a memory chip having a bad lower wafer and a good upper wafer in the chip, the address CKE0 terminal, ODT0 terminal, CS0 terminal of the memory chip are disposed on the upper wafer, the CKE1 terminal, ODT1 terminal, and CS1 terminal are disposed on the lower wafer, the driving module comprises a resistor RA1, a resistor RA5, a resistor RB1, a resistor RB5, a resistor RC1, a resistor RC5, and two wires, the RCDIMMKE 0 terminal of the DIMM module is connected to the input terminal of the resistor RA1, the output terminal of the resistor RA1 is connected to the address CKE0 terminal of the memory chip, the VSS terminal of the DIMM module is connected to the input terminal of the resistor RA5, the output terminal of the resistor RA5 is connected to the address CKE1 terminal of the memory chip, the RORB 0 terminal of the DIMM module is connected to the input terminal of the resistor RA1, the output end of the resistor RB1 is connected with an address ODT0 terminal of the memory chip, the VSS terminal of the DIMM module is connected with the input end of the resistor RB5, the output end of the resistor RB5 is connected with the address ODT1 terminal of the memory chip, the RS0_ N terminal of the DIMM module is connected with the input end of the resistor RC1, the output end of the resistor RC1 is connected with the address CS0 terminal of the memory chip, the VDD terminal of the DIMM module is connected with the input end of the resistor RC5, the output end of the resistor RC5 is connected with the address CS1 terminal of the memory chip, the VSS terminal of the DIMM module is connected with the VSS terminal of the memory chip through one conducting wire of the driving module, and the VDD terminal of the DIMM module is connected with the VDD terminal of the memory chip through the other conducting wire of the driving module.

3. The twinned crystal-changed memory module as claimed in claim 1, wherein the memory chip is a memory chip having a bad upper wafer and a good lower wafer in the chip, the address CKE0 terminal, ODT0 terminal, CS0 terminal of the memory chip are disposed on the upper wafer, the CKE1 terminal, ODT1 terminal, and CS1 terminal are disposed on the lower wafer, the driving module comprises a resistor RA2, a resistor RA3, a resistor RB2, a resistor RB3, a resistor RC2, a resistor RC3, and two wires, the RCKE DIMM 0 terminal of the DIMM module is connected to the input terminal of the resistor RA3, the output terminal of the resistor RA3 is connected to the address CKE1 terminal of the memory chip, the VSS terminal of the DIMM module is connected to the input terminal of the resistor RA2, the output terminal of the resistor RA2 is connected to the address CKE0 terminal of the memory chip, the RODT0 terminal of the DIMM module is connected to the input terminal of the resistor 3, the output end of the resistor RB3 is connected with an address ODT1 terminal of the memory chip, the VSS terminal of the DIMM module is connected with the input end of the resistor RB2, the output end of the resistor RB2 is connected with the address ODT0 terminal of the memory chip, the RS0_ N terminal of the DIMM module is connected with the input end of the resistor RC3, the output end of the resistor RC3 is connected with the address CS1 terminal of the memory chip, the VDD terminal of the DIMM module is connected with the input end of the resistor RC2, the output end of the resistor RC2 is connected with the address CS0 terminal of the memory chip, the VSS terminal of the DIMM module is connected with the VSS terminal of the memory chip through one conducting wire of the driving module, and the VDD terminal of the DIMM module is connected with the VDD terminal of the memory chip through the other conducting wire of the driving module.

4. The twin-crystal to single-crystal memory module according to claim 2 or 3, wherein the VDD voltage is a positive voltage.

5. The twin crystal to single crystal memory module as claimed in claim 1, wherein the memory chips are DDR4 memory chips.

6. The twin crystal to single crystal memory module as claimed in claim 1, wherein the number of the memory chips is eight or nine or sixteen or eighteen.