CN215007528U - Left-right split-bit memory module - Google Patents
Left-right split-bit memory module Download PDFInfo
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- CN215007528U CN215007528U CN202121171486.7U CN202121171486U CN215007528U CN 215007528 U CN215007528 U CN 215007528U CN 202121171486 U CN202121171486 U CN 202121171486U CN 215007528 U CN215007528 U CN 215007528U
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Abstract
The utility model discloses a control branch position memory module, it includes: the device comprises a memory unit, a variable power supply module, a driving module and a circuit board, wherein the memory unit, the variable power supply module and the driving module are all connected to the circuit board; the memory unit comprises at least four memory chip units, each memory chip unit consists of a first memory chip and a second memory chip, and the first memory chip and the second memory chip are the same damaged memory chips; the first memory chip and the second memory chip are respectively provided with row addressing A15, A16 and A17 terminals, the row addressing A15, A16 and A17 terminals of the first memory chip respectively correspond to the row addressing A15, A16 and A17 terminals of the second memory chip, the row addressing A15, A16 and A17 terminals of the first memory chip are respectively connected with three input ends of the driving module, three output ends of the driving module are correspondingly connected with the row addressing A15, A16 and A17 terminals of the second memory chip, and a power supply end of the driving module is connected with an output end of the variable power supply module. The chip is fully utilized, and the cost is reduced.
Description
Technical Field
The utility model relates to a memory chip module technical field, concretely relates to control reposition of redundant personnel memory module.
Background
With the rapid development of electronic products, many electronic products need to be applied to a memory chip to store data information. The memory module is reasonably arranged on the PCB so as to achieve the function of storing data of the memory module. At present, in the production test process of the memory module, a part of bad chips can inevitably occur, the bad chips can have a bad defect address range, and the bad chips can not realize all functions due to certain defects, and are often discarded, so that the waste of the chips is caused.
Therefore, in view of the above problems, the conventional chip module needs to be further improved.
SUMMERY OF THE UTILITY MODEL
The purpose of the utility model is to overcome the waste problem of bad memory chips, to the memory chips of bad defect address range appearing in the normal test process, through the concatenation circuit technology of memory cell, after recombining bad memory chips, rationally arrange on the circuit board, can obtain the memory module after the concatenation; specifically, the memory chip unit with the damaged memory chip is adopted and connected with the driving module, the driving module is connected with the variable power supply module, the output voltage is changed through the variable power supply module, the output voltage is transmitted to the driving module and then transmitted to the memory chip unit, and the memory chips in the memory chip unit can be spliced; the first memory chip and the second memory chip in the memory chip unit are adopted, and the line addressing A15 terminal, the A16 terminal and the A17 terminal are respectively connected with the driving module, so that the splicing of the same damaged memory chips can be effectively realized, and the bad memory chips are reused.
The technical scheme of the utility model is specifically as follows:
a left and right side-by-side split-bit memory module, comprising: the device comprises a memory unit, a variable power supply module, a driving module and a circuit board, wherein the memory unit, the variable power supply module and the driving module are all connected to the circuit board;
the memory unit comprises at least four memory chip units, at least one memory chip unit is formed by combining a first memory chip and a second memory chip, the first memory chip and the second memory chip are the same damaged memory chips, and the same damaged memory chips are the memory chips damaged in the left half part or the memory chips damaged in the right half part in the chip;
the first memory chip and the second memory chip are respectively provided with a row addressing A15 terminal, a16 terminal and a17 terminal, the row addressing A15 terminal, the A16 terminal and the A17 terminal of the first memory chip respectively correspond to the row addressing A15 terminal, the A16 terminal and the A17 terminal of the second memory chip, the row addressing A15 terminal, the A16 terminal and the A17 terminal of the first memory chip are respectively connected with three input ends of the driving module, three output ends of the driving module are correspondingly connected with the row addressing A15 terminal, the A16 terminal and the A17 terminal of the second memory chip, and a power supply end of the driving module is connected with the output end of the variable power supply module.
Further, the variable power module is a power supply capable of providing a VSS voltage, the VSS voltage is a voltage of a circuit common ground, the driving module includes a resistor R6 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips damaged in the right half of the chip, one end of the resistor R6 is connected in parallel to the row addressing a17 terminal of the first memory chip and the row addressing a17 terminal of the second memory chip, the other end of the resistor R6 is connected to an output terminal of the VSS power supply, and the row addressing a15 and a16 terminals of the first memory chip are respectively connected to the row addressing a15 and a16 terminals of the second memory chip.
Further, variable power module is the power that can provide the VDD voltage, the VDD voltage is the inside operating voltage of device, drive module includes a resistance R5 and three wire, three wire is connected respectively drive module's three input and the three output that corresponds, first memory chip and second memory chip are the memory chip of half damage on the left side inside the chip, resistance R5's one end parallel connection the row addressing A17 terminal of first memory chip with the row addressing A17 terminal of second memory chip, the output of the power of VDD is connected to resistance R5's the other end, the row addressing A15 and the A16 terminal of first memory chip correspond the connection respectively the row addressing A15 and the A16 terminal of second memory chip.
Further, the variable power module is a power supply capable of providing a VSS voltage, the VSS voltage is a voltage of a circuit common ground, the driving module includes a resistor R4 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips damaged in the right half of the chip, one end of the resistor R4 is connected in parallel to the row addressing a16 terminal of the first memory chip and the row addressing a16 terminal of the second memory chip, the other end of the resistor R4 is connected to an output terminal of the VSS power supply, and the row addressing a15 and a17 terminals of the first memory chip are respectively connected to the row addressing a15 and a17 terminals of the second memory chip.
Further, variable power module is the power that can provide the VDD voltage, the VDD voltage is the inside operating voltage of device, drive module includes a resistance R3 and three wire, three wire is connected respectively drive module's three input and the three output that corresponds, first memory chip and second memory chip are the memory chip of half damage on the left side inside the chip, resistance R3's one end parallel connection the row addressing A16 terminal of first memory chip with the row addressing A16 terminal of second memory chip, the output of the power of VDD is connected to resistance R3's the other end, the row addressing A15 and the A17 terminal of first memory chip correspond the connection respectively the row addressing A15 and the A17 terminal of second memory chip.
Further, the variable power module is a power supply capable of providing a VSS voltage, the VSS voltage is a voltage of a circuit common ground, the driving module includes a resistor R2 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips damaged in the right half of the chip, one end of the resistor R2 is connected in parallel to the row addressing a15 terminal of the first memory chip and the row addressing a15 terminal of the second memory chip, the other end of the resistor R2 is connected to an output terminal of the VSS power supply, and the row addressing a16 and a17 terminals of the first memory chip are respectively connected to the row addressing a16 and a17 terminals of the second memory chip.
Further, variable power module is the power that can provide the VDD voltage, the VDD voltage is the inside operating voltage of device, drive module is a resistance R1 and three wire, three wire is connected respectively drive module's three input and the three output that corresponds, first memory chip and second memory chip are the memory chip of half damage on the left side inside the chip, resistance R1's one end parallel connection the row addressing A15 terminal of first memory chip with the row addressing A15 terminal of second memory chip, the output of the power of VDD is connected to resistance R1's the other end, the row addressing A16 and the A17 terminal of first memory chip correspond the connection respectively the row addressing A16 and the A17 terminal of second memory chip.
Further, the VDD voltage is a positive voltage.
Further, in the memory unit, all the memory chip units are formed by combining a first memory chip and a second memory chip.
Further, the number of the memory chip units is 4 or 8.
Further, the memory chip is a DDR4 memory chip.
Advantageous effects
The utility model discloses a concatenation circuit technology of memory cell, after recombining bad memory chip, rationally arrange on the circuit board, can obtain the memory module after the concatenation; specifically, the memory chip unit with the damaged memory chip is adopted and connected with the driving module, the driving module is connected with the variable power supply module, the output voltage is changed through the variable power supply module, the output voltage is transmitted to the driving module and then transmitted to the memory chip unit, and the memory chips in the memory chip unit can be spliced; the first memory chip and the second memory chip in the memory chip unit are adopted, and the line addressing A15 terminal, the A16 terminal and the A17 terminal are respectively connected with the driving module, so that the splicing of the same damaged memory chips can be effectively realized, and the bad memory chips are reused.
In a specific embodiment, a power supply VDD is used to connect a matching circuit of a resistor R5 or a resistor R3 or a resistor R1, and the other end of the resistor R5 or the resistor R3 or the resistor R1 is connected in parallel to a corresponding row addressing a17 or a16 or a15 terminal of the first memory chip and a row addressing a17 or a16 or a15 terminal of the second memory chip, so that two bad memory chips (memory chips with good right and bad left) can work under the same power supply drive, memory modules with half-reduced memory capacity, unchanged speed and function, etc. can be effectively realized, the chips are fully utilized, and the cost is reduced.
In another specific embodiment, a power supply VSS is connected with a matching circuit of a resistor R6 or a resistor R4 or a resistor R2, and the other end of the resistor R6 or the resistor R4 or the resistor R2 is connected in parallel with a corresponding row addressing a17 or a16 or a15 terminal of the first memory chip and a row addressing a17 or a16 or a15 terminal of the second memory chip, so that two bad memory chips (memory chips with good left half and bad right half) can work under the same power supply drive, a memory module with half memory capacity, unchanged speed and function and the like can be effectively realized, the chips are fully utilized, and the cost is reduced.
Drawings
Fig. 1 is a schematic structural view of a left-right split-bit memory module according to the present invention.
Fig. 2 is a schematic diagram of the structure of the memory chip unit splicing of the left and right side-by-side memory module of the present invention.
Fig. 3 is the utility model relates to a structure schematic diagram of the concatenation of half good, half bad 16GB memory chip unit on the right side of left side of controlling a branch position memory module.
Fig. 4 is the utility model relates to a structure schematic diagram of about the concatenation of half good, half bad 16GB memory chip unit on a left side of right side of branch position memory module.
Fig. 5 is the utility model relates to a structure schematic diagram of about 8GB memory chip unit concatenation of branch position memory module good on the left side, bad on the right side.
Fig. 6 is the utility model relates to a structure schematic diagram of about 8GB memory chip unit concatenation of the right side half good, left side half bad of reposition of redundant personnel memory module.
Fig. 7 is the utility model relates to a control structural schematic of 4GB memory chip unit concatenation of branch position memory module left side half good, right side half bad.
Fig. 8 is the utility model relates to a control structural schematic of 4GB memory chip unit concatenation of half good, half bad on the left side of right side branch position memory module.
Fig. 9 is a block diagram illustrating internal selection of memory chips of the left-right multi-bit memory module according to the present invention.
Reference numerals: 1. a circuit board; 2. a memory unit; 3. a drive module; 4. a variable power supply module; 21. a first memory chip; 22. and a second memory chip.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.
Referring to fig. 1, the utility model provides a pair of control reposition of redundant personnel memory module, the memory module includes: the power supply comprises a memory unit 2, a variable power supply module 4, a driving module 3 and a circuit board 1, wherein the memory unit 2, the variable power supply module 4 and the driving module 3 are all connected to the circuit board 1;
the memory unit 2 comprises at least four memory chip units, at least one memory chip unit is formed by combining a first memory chip 21 and a second memory chip 22, the first memory chip 21 and the second memory chip 22 are the same damaged memory chips, and the same damaged memory chips are the memory chips damaged on the left half part or the memory chips damaged on the right half part in the chip;
referring to fig. 2, each of the first memory chip 21 and the second memory chip 22 is provided with a row addressing a15 terminal, an a16 terminal, and an a17 terminal, the row addressing a15 terminal, the a16 terminal, and the a17 terminal of the first memory chip 21 correspond to the row addressing a15 terminal, the a16 terminal, and the a17 terminal of the second memory chip 22, the row addressing a15 terminal, the a16 terminal, and the a17 terminal of the first memory chip 21 are connected to three input terminals of the driving module 3, three output terminals of the driving module 3 are connected to the row addressing a15 terminal, the a16 terminal, and the a17 terminal of the second memory chip 22, and a power source terminal of the driving module 3 is connected to an output terminal of the variable power source module 4.
In a first embodiment, referring to fig. 3, the variable power module 4 is a power supply capable of providing a VSS voltage, the VSS voltage is a voltage of a circuit common ground, the driving module 3 includes a resistor R6 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module 3, the first memory chip 21 and the second memory chip 22 are both memory chips with a damaged right half portion inside the chips, one end of the resistor R6 is connected in parallel to the row addressing a17 terminal of the first memory chip 21 and the row addressing a17 terminal of the second memory chip 22, the other end of the resistor R6 is connected to the output terminal of the VSS power supply, and the row addressing a15 and a16 terminals of the first memory chip 21 are respectively connected to the row addressing a15 and a16 terminals of the second memory chip 22.
In a second embodiment, referring to fig. 4, the variable power module 4 is a power supply capable of providing a VDD voltage, the VDD voltage is a working voltage inside a device, the driving module 3 includes a resistor R5 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module 3, the first memory chip 21 and the second memory chip 22 are both memory chips with damaged left half inside the chip, one end of the resistor R5 is connected in parallel to the row addressing a17 terminal of the first memory chip 21 and the row addressing a17 terminal of the second memory chip 22, the other end of the resistor R5 is connected to an output terminal of the VDD power supply, and the row addressing a15 and a16 terminals of the first memory chip 21 are respectively connected to the row addressing a15 and a16 terminals of the second memory chip 22.
In a third embodiment, referring to fig. 5, the variable power module 4 is a power supply capable of providing a VSS voltage, the VSS voltage is a voltage of a circuit common ground, the driving module 3 includes a resistor R4 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module 3, the first memory chip 21 and the second memory chip 22 are both memory chips with a damaged right half portion inside the chips, one end of the resistor R4 is connected in parallel to the row addressing a16 terminal of the first memory chip 21 and the row addressing a16 terminal of the second memory chip 22, the other end of the resistor R4 is connected to the output terminal of the VSS power supply, and the row addressing a15 and a17 terminals of the first memory chip 21 are respectively connected to the row addressing a15 and a17 terminals of the second memory chip 22.
In a fourth embodiment, referring to fig. 6, the variable power module 4 is a power supply capable of providing a VDD voltage, the VDD voltage is an internal operating voltage of the device, the driving module 3 includes a resistor R3 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module 3, the first memory chip 21 and the second memory chip 22 are both memory chips with damaged left half portions inside the chips, one end of the resistor R3 is connected in parallel to the row addressing a16 terminal of the first memory chip 21 and the row addressing a16 terminal of the second memory chip 22, the other end of the resistor R3 is connected to an output terminal of the VDD power supply, and the row addressing a15 and a17 terminals of the first memory chip 21 are respectively connected to the row addressing a15 and a17 terminals of the second memory chip 22.
In a fifth embodiment, referring to fig. 7, the variable power module 4 is a power supply capable of providing a VSS voltage, where the VSS voltage is a voltage of a circuit common ground, the driving module 3 includes a resistor R2 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module 3, the first memory chip 21 and the second memory chip 22 are both memory chips with a damaged right half portion inside the chips, one end of the resistor R2 is connected in parallel to the row addressing a15 terminal of the first memory chip 21 and the row addressing a15 terminal of the second memory chip 22, the other end of the resistor R2 is connected to the output terminal of the VSS power supply, and the row addressing a16 and a17 terminals of the first memory chip 21 are respectively connected to the row addressing a16 and a17 terminals of the second memory chip 22.
Sixth embodiment, referring to fig. 8, the variable power module 4 is a power supply capable of providing a VDD voltage, the VDD voltage is a working voltage inside a device, the driving module 3 is a resistor R1 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module 3, the first memory chip 21 and the second memory chip 22 are both memory chips with damaged left half inside the chips, one end of the resistor R1 is connected in parallel to the row addressing a15 terminal of the first memory chip 21 and the row addressing a15 terminal of the second memory chip 22, the other end of the resistor R1 is connected to an output terminal of the VDD power supply, and the row addressing a16 and a17 terminals of the first memory chip 21 are respectively connected to the row addressing a16 and a17 terminals of the second memory chip 22.
In the memory unit 2, all memory chip units are formed by combining a first memory chip 21 and a second memory chip 22; the VDD voltage is a positive voltage; the first memory chip 21 and the second memory chip 22 are DDR4 memory chips.
Referring to fig. 9, a block diagram of the selection of the internal memory module under good conditions is shown, where the area with the highest row address of 0 in the internal memory chip is set as the left half, and the area with the highest row address of 1 in the internal memory chip is set as the right half.
The utility model discloses implement the principle: by adopting the variable power module and the driving module and connecting the damaged memory chips in a specific mode, 8 similar bad chips can be spliced into a memory chip module with 4 capacities reduced by half and complete functions; 16 similar bad chips can be spliced into 8 memory chip modules with capacity halved and complete functions, and the like.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (10)
1. A left-right split-bit memory module, comprising: the device comprises a memory unit, a variable power supply module, a driving module and a circuit board, wherein the memory unit, the variable power supply module and the driving module are all connected to the circuit board;
the memory unit comprises at least four memory chip units, at least one memory chip unit is formed by combining a first memory chip and a second memory chip, the first memory chip and the second memory chip are the same damaged memory chips, and the same damaged memory chips are the memory chips damaged in the left half part or the memory chips damaged in the right half part in the chip;
the first memory chip and the second memory chip are respectively provided with a row addressing A15 terminal, a16 terminal and a17 terminal, the row addressing A15 terminal, the A16 terminal and the A17 terminal of the first memory chip respectively correspond to the row addressing A15 terminal, the A16 terminal and the A17 terminal of the second memory chip, the row addressing A15 terminal, the A16 terminal and the A17 terminal of the first memory chip are respectively connected with three input ends of the driving module, three output ends of the driving module are correspondingly connected with the row addressing A15 terminal, the A16 terminal and the A17 terminal of the second memory chip, and a power supply end of the driving module is connected with the output end of the variable power supply module.
2. The left-right split-bit memory module as claimed in claim 1, wherein the variable power module is a power supply capable of providing VSS voltage, the VSS voltage is a voltage at a circuit common ground, the driving module comprises a resistor R6 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips damaged at the right half portion inside the chips, one end of the resistor R6 is connected in parallel to the row addressing a17 terminal of the first memory chip and the row addressing a17 terminal of the second memory chip, the other end of the resistor R6 is connected to the output terminal of the VSS power supply, and the row addressing a15 and a16 terminals of the first memory chip are respectively connected to the row addressing a15 and a16 terminals of the second memory chip.
3. The left-right split-bit memory module according to claim 1, wherein the variable power module is a power supply capable of providing a VDD voltage, the VDD voltage is an internal operating voltage of a device, the driving module comprises a resistor R5 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips with damaged left half inside the chip, one end of the resistor R5 is connected in parallel to the row addressing a17 terminal of the first memory chip and the row addressing a17 terminal of the second memory chip, the other end of the resistor R5 is connected to an output terminal of the VDD power supply, and the row addressing a15 and a16 terminals of the first memory chip are respectively connected to the row addressing a15 and a16 terminals of the second memory chip.
4. The left-right split-bit memory module as claimed in claim 1, wherein the variable power module is a power supply capable of providing VSS voltage, the VSS voltage is a voltage at a circuit common ground, the driving module comprises a resistor R4 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips damaged at the right half portion inside the chips, one end of the resistor R4 is connected in parallel to the row addressing a16 terminal of the first memory chip and the row addressing a16 terminal of the second memory chip, the other end of the resistor R4 is connected to the output terminal of the VSS power supply, and the row addressing a15 and a17 terminals of the first memory chip are respectively connected to the row addressing a15 and a17 terminals of the second memory chip.
5. The left-right split-bit memory module according to claim 1, wherein the variable power module is a power supply capable of providing a VDD voltage, the VDD voltage is an internal operating voltage of a device, the driving module comprises a resistor R3 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips with damaged left half inside the chip, one end of the resistor R3 is connected in parallel to the row addressing a16 terminal of the first memory chip and the row addressing a16 terminal of the second memory chip, the other end of the resistor R3 is connected to an output terminal of the VDD power supply, and the row addressing a15 and a17 terminals of the first memory chip are respectively connected to the row addressing a15 and a17 terminals of the second memory chip.
6. The left-right split-bit memory module as claimed in claim 1, wherein the variable power module is a power supply capable of providing VSS voltage, the VSS voltage is a voltage at a circuit common ground, the driving module comprises a resistor R2 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips damaged at the right half portion inside the chips, one end of the resistor R2 is connected in parallel to the row addressing a15 terminal of the first memory chip and the row addressing a15 terminal of the second memory chip, the other end of the resistor R2 is connected to the output terminal of the VSS power supply, and the row addressing a16 and a17 terminals of the first memory chip are respectively connected to the row addressing a16 and a17 terminals of the second memory chip.
7. The left-right split-bit memory module according to claim 1, wherein the variable power module is a power supply capable of providing a VDD voltage, the VDD voltage is an internal operating voltage of a device, the driving module is a resistor R1 and three wires, the three wires are respectively connected to three input terminals and three corresponding output terminals of the driving module, the first memory chip and the second memory chip are both memory chips with damaged left half inside the chip, one end of the resistor R1 is connected in parallel to the row addressing a15 terminal of the first memory chip and the row addressing a15 terminal of the second memory chip, the other end of the resistor R1 is connected to an output terminal of the VDD power supply, and the row addressing a16 and a17 terminals of the first memory chip are respectively connected to the row addressing a16 and a17 terminals of the second memory chip.
8. The left-right split-bit memory module as claimed in claim 3, 5 or 7, wherein the VDD voltage is a positive voltage.
9. The left-right split-bit memory module according to claim 1, wherein all of the memory chip units are formed by combining a first memory chip and a second memory chip.
10. The left-right split-bit memory module according to claim 1, wherein the number of the memory chip units is 4 or 8.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121171486.7U CN215007528U (en) | 2021-05-28 | 2021-05-28 | Left-right split-bit memory module |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202121171486.7U CN215007528U (en) | 2021-05-28 | 2021-05-28 | Left-right split-bit memory module |
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| CN215007528U true CN215007528U (en) | 2021-12-03 |
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