CN216670717U - Solid state disk expansion circuit and solid state disk - Google Patents

Abstract

A solid state disk capacity expansion circuit and a solid state disk belong to the field of memories and comprise a control circuit, at least one multiplexing circuit and at least one storage circuit; each memory circuit includes a plurality of memory components; the control circuit outputs at least one series of digital signals and at least one series of selection signals from the line; each series of selection signals comprises a plurality of sets of selection signals; the multiplexing circuit selectively outputs a series of digital signals from a group of data output ends of the multiplexing circuit according to the plurality of groups of selection signals; the plurality of storage components of each storage circuit are correspondingly connected with the plurality of groups of data output ends of each multiplexing circuit one by one, and are connected with the control circuit to correspondingly receive the plurality of groups of selection signals of each series one by one; the capacity expansion of the solid state disk is realized, the number of parallel storage assemblies is reduced, and the load capacitance is reduced, so that the signal transmission rate is improved.

Description

Solid state disk expansion circuit and solid state disk

Technical Field

The application belongs to the field of memories, and particularly relates to a solid state disk capacity expansion circuit and a solid state disk.

Background

When the solid state disk is expanded from 2T to 8T, 16T or 32T, the hardware design is generally as follows: each channel of the control circuit of the 8T solid state disk is connected with 2 FLASH memory (FLASH) chips, each channel of the control circuit of the 16T solid state disk is connected with 4 FLASH chips, and each channel of the control circuit of the 32T solid state disk is connected with 8 FLASH chips. Each FLASH chip pin is provided with a load capacitor, the more FLASH chips are connected in parallel, the larger the load capacitor is, and the larger the load capacitor is, the signal transmission rate can be reduced due to the overlarge load capacitor, so that the signal transmission rate of the large-capacity solid state disk is reduced.

SUMMERY OF THE UTILITY MODEL

The application aims to provide a solid state disk capacity expansion circuit and a solid state disk, and aims to overcome the defect that the ground signal transmission rate is reduced due to the fact that a load capacitance is large in a traditional solid state disk capacity expansion circuit.

The embodiment of the application provides a solid state disk capacity expansion circuit, which comprises a control circuit, at least one multiplexing circuit and at least one storage circuit; each of the memory circuits includes a plurality of memory components;

the control circuit is configured to output at least one series of digital signals and at least one series of selection signals from a line; each series of said selection signals comprises a plurality of sets of said selection signals;

the multiplexing circuit is connected with the control circuit and is configured to selectively output a series of the digital signals from a group of data output ends of the multiplexing circuit according to a plurality of groups of the selection signals;

the plurality of memory components of each memory circuit are connected with the plurality of groups of data output ends of each multiplexing circuit in a one-to-one correspondence manner, and are connected with the control circuit to receive the plurality of groups of selection signals of each series in a one-to-one correspondence manner.

In one embodiment, each group of the selection signals comprises a plurality of subgroups of sub-selection signals, each of the memory components comprises a plurality of sub-memory circuits, and the plurality of sub-memory circuits receive a plurality of subgroups of the sub-selection signals in a one-to-one correspondence;

the sub-storage circuit is configured to perform a write operation according to the sub-selection signal of one of the subgroups and the digital signal when the digital signal is received.

In one embodiment, the sub-storage circuit includes a FLASH channel; the digital signal comprises a data signal and a control signal;

the FLASH channel comprises a series data signal input end, a series control signal input end and a small group selection signal input end;

the series of data signal input ends comprise ten data input and output ends of the FLASH channel;

the series of control signal input ends comprise six control signal input and output ends of the FLASH channel;

the one small group sub-selection signal input end comprises two sub-selection signal input ends of the FLASH channel.

In one embodiment, the memory circuit is a plurality of memory circuits, the plurality of memory circuits are arranged in a plurality of memory chips, and each memory chip at least comprises two sub-memory circuits belonging to two memory circuits respectively.

In one embodiment, the multiplexing circuit comprises a multiplexer;

the multiplexer comprises a plurality of groups of selection signal input ends, a plurality of groups of digital signal input ends and a plurality of groups of digital signal output ends;

wherein each set of select signal inputs comprises four sub-select signal inputs of the multiplexer;

the set of digital signal inputs comprises sixteen digital signal inputs of the multiplexer;

each set of digital signal outputs includes sixteen digital signal outputs of the multiplexer.

In one embodiment, the control circuit comprises a microprocessor;

the microprocessor comprises at least one series selection signal output end and at least one series digital signal output end; each series of select signal outputs comprises a plurality of sets of select signal outputs;

each group of selection signal output ends comprises four sub-selection signal output ends of the microprocessor;

each series of digital signal outputs comprises sixteen digital signal input outputs of the microprocessor.

The embodiment of the application further provides a solid state disk, which comprises the solid state disk capacity expansion circuit.

Compared with the prior art, the embodiment of the utility model has the following beneficial effects: because the multiplexing circuit selectively outputs a series of digital signals from a group of data output ends of the multiplexing circuit according to the plurality of groups of selection signals, and the plurality of storage assemblies of each storage circuit correspondingly receive the plurality of groups of selection signals of each series one by one, the capacity expansion of the solid state disk is realized, meanwhile, the parallel connection quantity of the storage assemblies is reduced, the load capacitance is reduced, and the signal transmission rate is improved.

Drawings

In order to more clearly illustrate the technical utility model in the embodiment of the present invention, the drawings used in the description of the embodiment will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

FIG. 1 is a schematic diagram of a related solid state disk expansion circuit;

fig. 2 is a schematic structural diagram of a solid state disk capacity expansion circuit according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a solid state disk expansion circuit storage device according to an embodiment of the present application;

fig. 4 is a schematic structural diagram of a solid state disk capacity expansion circuit according to an embodiment of the present application;

fig. 5 is a schematic diagram of a partial example of a multiplexing circuit in a solid state disk expansion circuit according to an embodiment of the present application;

fig. 6 is a schematic diagram of a part of an exemplary circuit of a multiplexing circuit in a solid state disk expansion circuit according to an embodiment of the present application;

fig. 7 is a schematic diagram of a partial example circuit of a sub-storage circuit in a solid state disk capacity expansion circuit according to an embodiment of the present disclosure;

fig. 8 is a schematic diagram of a partial example circuit of a control circuit in a solid state disk capacity expansion circuit according to an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a partial example circuit of a control circuit in a solid state disk expansion circuit according to an embodiment of the present disclosure.

Detailed Description

In order to make the technical problems, technical solutions and advantageous effects to be solved by the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

It will be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, refer to an orientation or positional relationship illustrated in the drawings for convenience in describing the present application and to simplify description, and do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present application.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.

The technical scheme of the related solid state disk capacity expansion circuit is as shown in fig. 1, and is characterized in that a controller and a FLASH memory (FLASH) are connected in sequence; wherein, the controller is respectively connected with each FLASH; the controller also comprises a Complex Programmable Logic Device (CPLD) Logic gate chip which is positioned between the controller and the FLASH and is respectively connected with the controller and the FLASH. Chip selection signals in each group of channels of the controller are connected to the logic input end of the CPLD logic gate chip, so that the number of the output chip selection signals is increased by the power of 2N; n is the number of chip selection signals input to the CPLD logic gate chip; the CPLD logic gate chip outputs doubled enable signals and then is directly connected with the FLASH, and the expansion of the storage capacity on hardware can be completed.

The technical scheme of the related solid state disk capacity expansion circuit needs to use a CPLD logic gate chip, and the hardware cost and the software development cost are high.

Fig. 2 is a schematic structural diagram of a solid state disk capacity expansion circuit according to a preferred embodiment of the present application, and for convenience of description, only parts related to this embodiment are shown, which are detailed as follows:

the solid state disk capacity expansion circuit comprises a control circuit 11, at least one multiplexing circuit 12 and at least one storage circuit; each memory circuit includes a plurality of memory components 13 i; the number of the storage components is n, n is a natural number, and i is a natural number smaller than or equal to n.

A control circuit 11 configured to output at least one series of digital signals and at least one series of selection signals from the lines; each series of select signals includes a plurality of sets of select signals.

And a multiplexing circuit 12 connected to the control circuit 11 and configured to selectively output a series of digital signals from a set of data output terminals of the multiplexing circuit 12 according to the plurality of sets of selection signals.

The plurality of memory components 13i of each memory circuit are connected to the plurality of sets of data output terminals of each multiplexing circuit 12 in a one-to-one correspondence, and are connected to the control circuit 11 to receive the plurality of sets of selection signals of each series in a one-to-one correspondence.

The memory component 13i is configured to perform a write operation according to a set of the selection signal and the digital signal when the digital signal is received.

In a specific implementation, each group of selection signals includes a plurality of sub-selection signals of the sub-groups, as shown in fig. 3, each memory component 13i includes a plurality of sub-memory circuits 13ij, and the plurality of sub-memory circuits 13ij receive the sub-selection signals of the plurality of sub-groups in a one-to-one correspondence; the sub memory circuit 13ij is configured to perform a write operation based on the sub selection signal of one of the subgroups and the digital signal when the digital signal is received. Each memory component 13i includes m sub-memory circuits 13ij, where m is a natural number, and j is a natural number less than or equal to m.

Each group of the selection signals comprises a plurality of subgroups of sub-selection signals, and each group of the storage assemblies 13i is expanded into a plurality of sub-storage circuits 13ij, so that the capacity expansion capacity of the solid state disk capacity expansion circuit is further improved.

In one example, the memory circuit is plural, and the plural memory circuits are provided in plural memory chips, each of which includes at least two sub memory circuits 13ij belonging to the two memory circuits, respectively.

For example, as shown in fig. 4, the digital signal is two series (Channel0 and Channel1), the selection signal is also two series, each series selection signal includes 4 sets of selection signals, there are two multiplexing circuits 12 and two memory circuits (the first memory circuit is connected to the first multiplexing circuit 12 by a solid line, and the second memory circuit is connected to the second multiplexing circuit 12 by a dotted line), each memory circuit includes 4 memory elements 13i, and each memory element 13i includes 2 sub-memory circuits 13 ij; each multiplexing circuit 12 includes 4 sets of data outputs, each set of data outputs connecting two of the sub-memory circuits 13ij, each sub-memory circuit 13ij including two DIEs, such as DIE0 and DIE2, or DIE1 and DIE 3. Wherein DIE refers to FLASH DIE.

The 4 groups of memory components 13i in each memory circuit are connected with the 4 groups of data output ends of each multiplexing circuit 12 in a one-to-one correspondence manner, and are connected with the control circuit 11 to receive 4 groups of selection signals in each series of selection signals in a one-to-one correspondence manner; the two memory circuits of the solid-state disk capacity expansion circuit are arranged in8 memory CHIPs (CHIP1 to CHIP8), each of which includes at least two sub-memory circuits 13ij belonging to the two memory circuits, respectively. Namely: the sub-memory circuits 13ij of the respective memory chips are connected to the multiplexer circuit 12 in an interleaved manner.

Each memory chip at least comprises two sub-memory circuits 13ij respectively belonging to the two memory circuits, so that when a single memory chip works, the configuration of a plurality of multiplexing circuits 12 can be used simultaneously, and the data transmission speed of the solid state disk capacity expansion circuit is improved.

In particular implementations, multiplexing circuit 12 includes a multiplexer U1; the multiplexer U1 includes a plurality of sets of select signal inputs, a plurality of digital signal inputs, and a plurality of sets of digital signal outputs.

Wherein each set of select signal inputs comprises four sub-select signal inputs of multiplexer U1; the set of digital signal inputs includes sixteen digital signal inputs of multiplexer U1; each set of digital signal outputs includes sixteen digital signal outputs of multiplexer U1.

As shown in FIG. 5, the first set of selection signal inputs of multiplexer U1 includes a first sub-selection signal input CIO0 of multiplexer U1, a second sub-selection signal input CIO1 of multiplexer U1, a third sub-selection signal input CIO2 of multiplexer U1, and a fourth sub-selection signal input CIO3 of multiplexer U1. The other group selection signal input ends are analogized, and the description is omitted here.

As shown IN FIG. 6, the set of digital signal inputs of the multiplexer U1 includes a first digital signal input IN0 of the multiplexer U1, a second digital signal input IN1 of the multiplexer U1, a third digital signal input IN2 of the multiplexer U1, a fourth digital signal input IN3 of the multiplexer U1, a fifth digital signal input IN4 of the multiplexer U1, a sixth digital signal input IN5 of the multiplexer U1, a seventh digital signal input IN6 of the multiplexer U1, and an eighth digital signal input IN7 of the multiplexer U1, a ninth digital signal input IN8 of the multiplexer U1, a tenth digital signal input IN9 of the multiplexer U1, an eleventh digital signal input IN10 of the multiplexer U1, a twelfth digital signal input IN 57 of the multiplexer U1, a thirteenth digital signal input IN12 of the multiplexer U1, a twelfth digital signal input IN11 of the multiplexer U3882, A fourteenth digital signal input IN13 of the multiplexer U1, a fifteenth digital signal input IN14 of the multiplexer U1, and a sixteenth digital signal input IN15 of the multiplexer U1.

As shown in FIG. 5, the first set of digital signal outputs of the multiplexer U1 includes an A-channel first data output A0 of the multiplexer U1, an A-channel second data output A1 of the multiplexer U1, an A-channel third data output A2 of the multiplexer U1, an A-channel fourth data output A3 of the multiplexer U1, an A-channel fifth data output A4 of the multiplexer U1, an A-channel sixth data output A5 of the multiplexer U1, an A-channel seventh data output A6 of the multiplexer U1, an A-channel eighth data output A7 of the multiplexer U1, an A-channel ninth data output A8 of the multiplexer U1, an A-channel tenth data output A9 of the multiplexer U1, an A-channel eleventh data output A10 of the multiplexer U1, an A-channel twelfth data output A11 of the multiplexer U1, and an A12 of the multiplexer U1, A-channel fourteenth data output terminal a13 of multiplexer U1, an a-channel fifteenth data output terminal a14 of multiplexer U1, and an a-channel sixteenth data output terminal a15 of multiplexer U1. And the rest groups of digital signal output ends are analogized, and the description is omitted here.

Fig. 5 to 6 are partial example circuit configuration diagrams of the multiplexer U1.

In a specific implementation, the sub-storage circuit 13ij includes a FLASH channel U2; the digital signal comprises a data signal and a control signal; FLASH channel U2 includes a series data signal input, a series control signal input, and a subgroup select signal input.

Wherein, a series of data signal input ends comprise ten data input and output ends of the FLASH channel U2; the series control signal input end comprises six control signal input and output ends of a FLASH channel; one subset of select signal inputs comprises the two sub-select signal inputs of FLASH channel U2.

As shown in fig. 7, one series of data signal input terminals of the FLASH channel U2 includes a first data input output terminal DQ0_0 of the FLASH channel U2, a second data input output terminal DQ1_0 of the FLASH channel U2, a third data input output terminal DQ2_0 of the FLASH channel U2, a fourth data input output terminal DQ3_0 of the FLASH channel U2, a fifth data input output terminal DQ4_0 of the FLASH channel U2, a sixth data input output terminal DQ5_0 of the FLASH channel U2, a seventh data input output terminal DQ6_0 of the FLASH channel U2, an eighth data input output terminal DQ7_0 of the FLASH channel U2, a positive data strobe terminal DQs _0_ T of the FLASH channel U2, and a negative data terminal DQs _0_ C of the FLASH channel U2.

One series control signal input terminal of the FLASH channel U2 includes the address latch terminal ALE _0 of the write protect terminal WP _0_ N, FLASH channel U2 of channel U2 of WE _0_ N, FLASH of the positive read enable terminal RE _0_ T, FLASH channel U2 of the FLASH channel U2 and the command latch terminal CLE _0 of the FLASH channel U2 of the negative read enable terminal RE _0_ C, FLASH channel U2.

A subgroup of sub-select signal inputs of the FLASH channel U2 includes a first enable terminal CE0_0_ N of the FLASH channel U2 and a second enable terminal CE1_0_ N of the FLASH channel U2.

In a specific implementation, the control circuit 11 includes a microprocessor U3; microprocessor U3 includes at least one serial select signal output and a plurality of serial digital signal outputs. Each series of select signal outputs includes a plurality of sets of select signal outputs.

Each group of the selection signal output ends comprises four sub-selection signal output ends of the microprocessor U3; each series of digital signal outputs comprises sixteen digital signal outputs of microprocessor U3;

as shown in fig. 8, the first series of first group selection signal outputs of the microprocessor U3 includes a first series of first enable signal outputs FC0_ CE00_ N of the microprocessor U3, a first series of second enable signal outputs FC0_ CE01_ N of the microprocessor U3, a first series of third enable signal outputs FC0_ CE02_ N of the microprocessor U3, and a first series of fourth enable signal outputs FC0_ CE03_ N of the microprocessor U3. The first series of other group select signal outputs of microprocessor U3 and the other series of group select signal outputs of microprocessor U3, and so on, will not be described again here.

As shown in FIG. 9, the first series of digital signal output terminals of microprocessor U3 includes a first series of first data input/output terminals FC0_ DQ0_ P of microprocessor U3, a first series of second data input/output terminals FC0_ DQ1_ P of microprocessor U3, a first series of third data input/output terminals FC0_ DQ2_ P of microprocessor U3, a first series of fourth data input/output terminals FC0_ DQ3_ P of microprocessor U3, a first series of fifth data input/output terminals FC0_ DQ4_ P of microprocessor U3, a first series of sixth data input/output terminals FC0_ DQ5_ P of microprocessor U3, a first series of seventh data input/output terminals 5_ DQ _ P of microprocessor U5, a first series of eighth data input/output terminals FC 4_ DQ5_ P of microprocessor U5, and a first series of DQS 5_ FC 5_ DQS _ P of microprocessor U5, The microprocessor U3 includes a negative data strobe terminal FC0_ DQS _ PC, a first series of address latch terminals FC0_ ALE _ P of the microprocessor U3, a first series of command latch terminals FC0_ CLE _ P of the microprocessor U3, a first series of write enable terminals FC0_ WE _ N of the microprocessor U3, a first series of positive read enable terminals FC0_ RE _ NT of the microprocessor U3, a first series of negative read enable terminals FC0_ RE _ NC of the microprocessor U3, and a first series of write protect terminals FC0_ ODT _ N of the microprocessor U3. The other sets of digital signal outputs of microprocessor U3 and so on will not be described in detail herein.

Fig. 8 to 9 are partial example circuit configuration diagrams of the microprocessor U3.

The following further description of fig. 5 to 9 is made in conjunction with the working principle:

microprocessor U3 outputs at least one series digital signal from at least one series digital signal output and at least one series selection signal from at least one series selection signal output; each series of selection signals comprises a plurality of sets of selection signals; as shown in fig. 9, the first series of digital signals are selected from a first series of first data input/output terminals FC0_ DQ0_ P of the microprocessor U3, a first series of second data input/output terminals FC0_ DQ1_ P of the microprocessor U3, a first series of third data input/output terminals FC0_ DQ2_ P of the microprocessor U3, a first series of fourth data input/output terminals FC0_ DQ3_ P of the microprocessor U3, a first series of fifth data input/output terminals FC0_ DQ4_ P of the microprocessor U3, a first series of sixth data input/output terminals FC0_ DQ5_ P of the microprocessor U3, a first series of seventh data input/output terminals FC0_ DQ6_ P of the microprocessor U3, a first series of eighth data input/output terminals FC0_ DQ7_ P of the microprocessor U3, and a first series of positive data input/output terminals FC 5_ DQs _0_ P of the microprocessor U3, The microprocessor U3 includes a negative data strobe terminal FC0_ DQS _ PC, a first series of address latch terminals FC0_ ALE _ P of the microprocessor U3, a first series of command latch terminals FC0_ CLE _ P of the microprocessor U3, a first series of write enable terminals FC0_ WE _ N of the microprocessor U3, a first series of positive read enable terminals FC0_ RE _ NT of the microprocessor U3, a first series of negative read enable terminals FC0_ RE _ NC of the microprocessor U3, and a first series of write protect terminals FC0_ ODT _ N output of the microprocessor U3.

As shown in fig. 8, the first series of first group selection signals are output from the first series of first enable signal output terminals FC0_ CE00_ N of the microprocessor U3, the first series of second enable signal output terminals FC0_ CE01_ N of the microprocessor U3, the first series of third enable signal output terminals FC0_ CE02_ N of the microprocessor U3, and the first series of fourth enable signal output terminals FC0_ CE03_ N of the microprocessor U3.

At least one multiplexer U1 receives the at least one series digital signal and the at least one series select signal, respectively.

One set of digital signal inputs of each multiplexer U1 receives each series of digital signals and multiple sets of select signal inputs of each multiplexer U1 receives each series of select signals. As shown in FIG. 5, the first set of selection signals of the multiplexer U1 are received by the first selection signal input CIO0 of the multiplexer U1, the second selection signal input CIO1 of the multiplexer U1, the third selection signal input CIO2 of the multiplexer U1, and the fourth selection signal input CIO3 of the multiplexer U1. As shown IN FIG. 6, each series of digital signals consists of a first digital signal input IN0 of the multiplexer U1, a second digital signal input IN1 of the multiplexer U1, a third digital signal input IN2 of the multiplexer U1, a fourth digital signal input IN3 of the multiplexer U1, a fifth digital signal input IN4 of the multiplexer U1, a sixth digital signal input IN5 of the multiplexer U1, a seventh digital signal input IN6 of the multiplexer U1, an eighth digital signal input IN7 of the multiplexer U1, a ninth digital signal input IN8 of the multiplexer U1, a tenth digital signal input IN9 of the multiplexer U1, an eleventh digital signal input IN10 of the multiplexer U1, a twelfth digital signal input IN11 of the multiplexer U1, a thirteenth digital signal input IN12 of the multiplexer U1, a fourteenth digital signal input IN6 of the multiplexer U1, a fourteenth digital signal input IN13 of the multiplexer U1, The fifteenth digital signal input IN14 of the multiplexer U1 and the sixteenth digital signal input IN15 of the multiplexer U1.

Each multiplexer U1 selectively outputs a series of digital signals from a set of data outputs of the multiplexer U1 according to a plurality of sets of select signals. When digital signals are output from the first group of digital signal outputs of the multiplexer U1, as shown in fig. 5, the digital signals are specifically output from the a-channel first data output a0 of the multiplexer U1, the a-channel second data output a1 of the multiplexer U1, the a-channel third data output a2 of the multiplexer U1, the a-channel fourth data output A3 of the multiplexer U1, the a-channel fifth data output a4 of the multiplexer U1, the a-channel sixth data output A5 of the multiplexer U1, the a-channel seventh data output A6 of the multiplexer U1, the a-channel eighth data output A7 of the multiplexer U1, the a-channel ninth data output A8 of the multiplexer U1, the a-channel tenth data output a9 of the multiplexer U1, the a-channel eleventh data output a10 of the multiplexer U1, and the a-channel twelfth data output a11 of the multiplexer U1, An A-channel thirteenth data output terminal A12 of the multiplexer U1, an A-channel fourteenth data output terminal A13 of the multiplexer U1, an A-channel fifteenth data output terminal A14 of the multiplexer U1, and an A-channel sixteenth data output terminal A15 of the multiplexer U1.

The digital signals include data signals and control signals.

Each set of selection signals includes a plurality of sub-set selection signals, as shown in FIG. 7, the first enable CE0_0_ N of the FLASH channel U2 and the second enable CE1_0_ N of the FLASH channel U2 receive one sub-set selection signal, and when the first data input output DQ0_0 of the FLASH channel U2, the second data input output DQ1_0 of the FLASH channel U2, the third data input output 84DQ 53 _0 of the FLASH channel U2, the fourth data input output DQ3_0 of the FLASH channel U2, the fifth data input output DQ4_0 of the FLASH channel U2, the sixth data input output DQ5_0 of the FLASH channel U2, the seventh data input output DQ6_0 of the FLASH channel U2 and the eighth data input output DQ7_0 of the FLASH channel U2, the first series positive data input selection end DQ0_ FC of the microprocessor 3, the negative data input DQ FC 4972 _ FC, and the first series of the microprocessor 6474 _ P0 receive the first data input signal, When the first series of command latch terminals FC0_ CLE _ P of the microprocessor U3, the first series of write enable terminals FC0_ WE _ N of the microprocessor U3, the first series of positive read enable terminals FC0_ RE _ NT of the microprocessor U3, the first series of negative read enable terminals FC0_ RE _ NC of the microprocessor U3, and the first series of write protect terminals FC0_ ODT _ N of the microprocessor U3 receive the control signals, the FLASH channel U2 performs the write operation according to one subgroup selection signal and the digital signal.

The embodiment of the utility model also provides the solid state disk, which comprises the solid state disk capacity expansion circuit.

The embodiment of the utility model comprises a control circuit, at least one multiplexing circuit and at least one storage circuit; each memory circuit includes a plurality of memory components; the control circuit outputs at least one series of digital signals and at least one series of selection signals from the line; each series of selection signals comprises a plurality of sets of selection signals; the multiplexing circuit selectively outputs a series of digital signals from a set of data output terminals of the multiplexing circuit according to the plurality of sets of selection signals; the plurality of storage components of each storage circuit are correspondingly connected with the plurality of groups of data output ends of each multiplexing circuit one by one, and are connected with the control circuit to correspondingly receive the plurality of groups of selection signals of each series one by one; because the multiplexing circuit selectively outputs a series of digital signals from a group of data output ends of the multiplexing circuit according to the plurality of groups of selection signals, and the plurality of storage assemblies of each series of storage circuits correspondingly receive the plurality of groups of selection signals of each series one by one, the capacity expansion of the solid state disk is realized, meanwhile, the parallel connection quantity of the storage assemblies is reduced, the load capacitance is reduced, and the signal transmission rate is improved.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims (7)

1. A solid state disk capacity expansion circuit is characterized by comprising a control circuit, at least one multiplexing circuit and at least one storage circuit; each of the memory circuits includes a plurality of memory components;

the control circuit is configured to output at least one series of digital signals and at least one series of selection signals from a line; each series of said selection signals comprises a plurality of sets of said selection signals;

the multiplexing circuit is connected with the control circuit and is configured to selectively output a series of the digital signals from a group of data output ends of the multiplexing circuit according to a plurality of groups of the selection signals;

the plurality of memory components of each memory circuit are connected with the plurality of groups of data output ends of each multiplexing circuit in a one-to-one correspondence manner, and are connected with the control circuit to receive the plurality of groups of selection signals of each series in a one-to-one correspondence manner.

2. The flash memory circuit of claim 1, wherein each group of said selection signals comprises a plurality of subgroups of sub-selection signals, each said memory component comprises a plurality of sub-memory circuits, and a plurality of said sub-memory circuits receive a plurality of subgroups of said sub-selection signals in a one-to-one correspondence;

the sub-storage circuit is configured to perform a write operation according to the sub-selection signal of one of the subgroups and the digital signal when the digital signal is received.

3. The solid state disk capacity expansion circuit of claim 2, wherein the sub-storage circuit comprises a FLASH channel; the digital signal comprises a data signal and a control signal;

the FLASH channel comprises a series data signal input end, a series control signal input end and a small group selection signal input end;

the serial digital signal input end comprises ten data input and output ends of the FLASH channel;

the series of control signal input ends comprise six control signal input and output ends of the FLASH channel;

the one small group sub-selection signal input end comprises two sub-selection signal input ends of the FLASH channel.

4. The solid state disk capacity expansion circuit of claim 2, wherein the storage circuit is a plurality of storage circuits, the plurality of storage circuits are arranged in a plurality of storage chips, and each storage chip comprises at least two sub-storage circuits belonging to two storage circuits respectively.

5. The solid state disk capacity expansion circuit of claim 1, wherein the multiplexing circuit comprises a multiplexer;

the multiplexer comprises a plurality of groups of selection signal input ends, a plurality of groups of digital signal input ends and a plurality of groups of digital signal output ends;

wherein each set of select signal inputs comprises four sub-select signal inputs of the multiplexer;

the set of digital signal inputs comprises sixteen digital signal inputs of the multiplexer;

each set of digital signal outputs includes sixteen digital signal outputs of the multiplexer.

6. The solid state disk capacity expansion circuit of claim 1, wherein the control circuit comprises a microprocessor;

the microprocessor comprises at least one series selection signal output end and at least one series digital signal output end; each series of select signal outputs comprises a plurality of sets of select signal outputs;

each group of selection signal output ends comprises four sub-selection signal output ends of the microprocessor;

each series of digital signal outputs comprises sixteen digital signal input outputs of the microprocessor.

7. A solid state disk, characterized in that the solid state disk comprises the solid state disk capacity expansion circuit of any one of claims 1 to 6.

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