CN215577704U - Novel memory module with upper part and lower part separated - Google Patents
Novel memory module with upper part and lower part separated Download PDFInfo
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- CN215577704U CN215577704U CN202121750642.5U CN202121750642U CN215577704U CN 215577704 U CN215577704 U CN 215577704U CN 202121750642 U CN202121750642 U CN 202121750642U CN 215577704 U CN215577704 U CN 215577704U
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Abstract
The utility model relates to the technical field of memory modules, and discloses a novel upper and lower position-division memory module, which comprises: the memory chip module and the partition driving unit are connected to the circuit board; the input end of the partition driving unit is provided with two terminals, the input end of the partition driving unit is connected with a power supply on the circuit board, the output end of the partition driving unit is provided with two terminals, the first output end of the partition driving unit is connected with a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip in parallel, the second output end of the partition driving unit is connected with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip in parallel, and the partition driving unit is used for providing high levels or low levels of the BG0 terminal or the BG1 terminal of the first memory chip and the BG0 terminal or the BG1 terminal of the second memory chip. By means of the circuit splicing technology, the memory chip is fully utilized, and cost is reduced.
Description
Technical Field
The utility model relates to the technical field of memory chip modules, in particular to a novel upper and lower split-bit memory module.
Background
With the rapid development of electronic products, many electronic products need to be applied to a memory chip to store data information. The memory module is reasonably arranged on the PCB so as to achieve the function of storing data of the memory module. At present, in the production test process of the memory module, a part of bad chips can inevitably occur, the bad chips can have a bad defect address range, and the bad chips can not realize all functions due to certain defects, and are often discarded, so that the waste of the chips is caused. If the memory chips with the defects are utilized and reasonably spliced, the cost of the memory module can be reduced. The memory chip is stored in the upper half part and the lower half part, if the upper half part or the lower half part is poor, the memory chip needs to be spliced and combined, and a fixed circuit is adopted for splicing, so that the production cost of the memory module can be reduced.
Therefore, in view of the above problems, the conventional chip module needs to be further improved to reuse the defective memory chip.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the problem of waste of bad memory chips, and the memory chips with bad defect address ranges in the normal test process are reasonably arranged on a circuit board after being recombined through the splicing circuit technology of a first memory chip and a second memory chip so as to obtain a spliced memory module; specifically, a BG0 terminal or a BG1 terminal with a bad memory chip is connected with the output end of the partition driving unit, and the partition driving unit can provide a BG0 terminal or a BG1 terminal of the memory chip with a high level or a low level to realize the combination of the memory chips; the BG0 terminal of the first memory chip is connected with the BG0 terminal of the second memory chip, or the BG1 terminal of the first memory chip is connected with the BG1 terminal of the second memory chip, and then the high level or the low level is output by the partition driving unit, so that the combination of the memory chips can be effectively realized, and the bad memory chips can be reused.
The technical scheme of the utility model is as follows:
the utility model provides a novel divide bit memory module from top to bottom, memory module includes: the memory chip module and the partition driving unit are connected to the circuit board; the memory chip module comprises eight or sixteen memory chip units, each memory chip unit comprises a first memory chip and a second memory chip, the first memory chip and/or the second memory chip are memory chips with bad defect addresses, the first memory chip and the second memory chip are both provided with BG0 terminals and BG1 terminals, and the first memory chip and the second memory chip are both provided with BG0 regions and BG1 regions; the first memory chip and the second memory chip are both DDR4 memory chips; the input end of the partition driving unit is provided with two terminals, the first input end of the partition driving unit is connected with the positive electrode of a power supply on the circuit board, the second input end of the partition driving unit is connected with the negative electrode of the power supply on the circuit board, the output end of the partition driving unit is provided with two terminals, the first output end of the partition driving unit is connected with the BG0 terminal of the first memory chip and the BG0 terminal of the second memory chip in parallel and used for providing high level or low level for the BG0 terminal of the first memory chip and the BG0 terminal of the second memory chip; the second output end of the partition driving unit is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, and is used for providing a high level or a low level for a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip.
Further, the first memory chip is a memory chip with a BG1 area having a bad defect address, the second memory chip is a memory chip with a BG1 area having a bad defect address, the partition driving unit includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D4, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel to one end of a resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, another end of the resistor R1 is connected in parallel to a base of the transistor Q1 and a cathode of the diode D1, an anode of the diode D1 is connected in parallel to one end of the resistor R1 and an anode of a power supply, an emitter of the transistor Q1 is connected to one end of the resistor R1, another end of the power supply is connected to a cathode of the resistor R1, the collector of the triode Q1 is connected in parallel with the other end of the resistor R4, the anode of the diode D4, the anode of the diode D2 and one end of the resistor R6, the other end of the resistor R6 is connected with the emitter of the triode Q3, the base of the triode Q3 is in an off state, the cathode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected in parallel with the collector of the triode Q2, the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip, the cathode of the diode D2 is connected with the base of the triode Q2, the emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the cathode of the power supply.
Further, the first memory chip is a memory chip with a BG0 area bad defect address, the second memory chip is a memory chip with a BG0 area bad defect address, the partition driving unit includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D3, a diode D4, a triode Q1, a triode Q2, and a triode Q3, a collector of the triode Q3 is connected in parallel with one end of the resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 is connected in parallel with an anode of the diode D3, a base of the triode Q1, and a cathode of the diode D1, a cathode of the diode D1 is connected in parallel with one end of the resistor R4 and an anode of the power supply, and an emitter of the transistor Q1 is connected with an emitter of the resistor R5, the other end of the resistor R5 is connected with the negative electrode of a power supply, the collector of the triode Q1 is connected with the other end of the resistor R4, the anode of the diode D4, the anode of the diode D2 and one end of the resistor R6 in parallel, the other end of the resistor R6 is connected with the emitter of the triode Q3, the cathode of the diode D3 is connected with the base of the triode Q3, the cathode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the collector of the triode Q2, the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip in parallel, the cathode of the diode D2 is connected with the base of the triode Q2, the emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the negative electrode of the power supply.
Further, the first memory chip is a memory chip with a BG1 area bad defect address, the second memory chip is a memory chip with a BG1 area bad defect address, the partition driving unit includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D2, a diode D4, a diode D3, a triode Q1, a triode Q2, and a triode Q3, a collector of the triode Q3 is connected in parallel with one end of the resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 and the anode of the diode D3 are in an off state, one end of the resistor R4 is connected with the anode of a power supply, a base of the triode Q1 is in an off state, an emitter of the triode Q1 is connected with one end of the resistor R5, the other end of the resistor R5 is connected with the cathode of the power supply, the collector of the triode Q1 is connected in parallel with the other end of the resistor R4, the anode of the diode D4, the anode of the diode D2 and one end of the resistor R6, the other end of the resistor R6 is connected with the emitter of the triode Q3, the base of the triode Q3 is connected with the cathode of the diode D3, the cathode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected in parallel with the collector of the triode Q2, the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip, the cathode of the diode D2 is connected with the base of the transistor Q2, the emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the cathode of the power supply.
Further, the first memory chip is a memory chip with a BG0 area bad defect address, the second memory chip is a memory chip with a BG0 area bad defect address, the partition driving unit includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D3, a diode D4, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel with one end of the resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 and an anode of the diode D3 are in an off state, one end of the resistor R4 is connected with an anode of a power supply, an emitter of the transistor Q1 is connected with one end of the resistor R5, the other end of the resistor R5 is connected with a cathode of the power supply, and the other end of the transistor Q1 is connected with a collector of the resistor R4 in parallel with a cathode of the second memory chip, The diode comprises a diode D4 and one end of a resistor R6, the other end of the resistor R6 is connected with an emitter of the triode Q3, the cathode of the diode D3 is connected with a base of the triode Q3, the cathode of the diode D4 is connected with one end of a resistor R2, the other end of the resistor R2 is connected with a collector of the triode Q2, a BG1 terminal of a first memory chip and a BG1 terminal of a second memory chip in parallel, the base of the triode Q2 is in an off state, the emitter of the triode Q2 is connected with one end of a resistor R3, and the other end of the resistor R3 is connected with the cathode of a power supply.
By adopting the diode, whether the base electrode of the triode is conducted or not can be realized through the diode, and the diode is burnt out or directly taken out for processing for realizing disconnection of the base electrode of the triode. By adopting the partition driving unit, single-path operation can be realized to drive the BGO terminal of the memory chip or the BG1 terminal of the memory chip to be at high level or low level.
Further, the first memory chip is a bad memory chip or a good memory chip, and the second memory chip is a bad memory chip or a good memory chip.
Further, the circuit board is a PCB circuit board.
Advantageous effects
According to the utility model, by adopting the splicing circuit technology of the first memory chip and the second memory chip, after the bad memory chips are recombined, the memory chips are reasonably arranged on the circuit board, and a spliced memory module can be obtained; specifically, a BG0 terminal or a BG1 terminal with a bad memory chip is connected with the output end of the partition driving unit, and the partition driving unit can provide a BG0 terminal or a BG1 terminal of the memory chip with a high level or a low level to realize the combination of the memory chips; the BG0 terminal of the first memory chip is connected with the BG0 terminal of the second memory chip, or the BG1 terminal of the first memory chip is connected with the BG1 terminal of the second memory chip, and then the high level or the low level is output by the partition driving unit, so that the combination of the memory chips can be effectively realized, and the bad memory chips can be reused. The conduction or the cut-off of the diode is adopted to realize the conduction or the cut-off of the triode, so that the high level or the low level of the memory chip is provided; the partition driving unit can provide high level or low level of the memory chip by using a fixed circuit.
Drawings
Fig. 1 is a schematic structural diagram of a novel vertical split-bit memory module according to the present invention.
Fig. 2 is a block diagram illustrating an internal chip selection of a novel vertical split-bit memory module according to the present invention.
Reference numerals: 1. a first memory chip; 2. a second memory chip; 3. and a partition driving unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, the present invention provides a novel upper and lower split-bit memory module, which includes: the memory chip module and the partition driving unit are connected to the circuit board. In this embodiment, the circuit board is a PCB circuit board.
The memory chip module is eight or sixteen memory chip units, each memory chip unit comprises the first memory chip 1 and the second memory chip 2, the first memory chip 1 and/or the second memory chip 2 are memory chips with bad defect addresses, the first memory chip 1 and the second memory chip 2 are both provided with BG0 terminals and BG1 terminals, and the first memory chip and the second memory chip are both provided with BG0 regions and BG1 regions. In this embodiment, the first memory chip 1 and the second memory chip 2 are both DDR4 memory chips.
The input of subregion drive unit 3 is equipped with two terminals, the positive pole of the last power of subregion drive unit's first input connecting circuit board, the negative pole of the last power of subregion drive unit's second input connecting circuit board, subregion drive unit's output is equipped with two terminals, subregion drive unit's first output parallel connection first memory chip's BG0 terminal and second memory chip's BG0 terminal for provide high level or low level for the BG0 terminal of first memory chip 1 and the BG0 terminal of second memory chip 2. The second output end of the partition driving unit is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, and is used for providing a high level or a low level for the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip.
In a first embodiment, the first memory chip 1 is a BG1 area bad defect address memory chip, the second memory chip 2 is a BG1 area bad defect address memory chip, the partition driving unit 3 includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D4, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel to one end of a resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, another end of the resistor R1 is connected in parallel to a base of the transistor Q1 and a cathode of the diode D1, an anode of the diode D1 is connected in parallel to one end of the resistor R4 and an anode of a power supply, an emitter of the transistor Q1 is connected to one end of the resistor R5, the other end of the resistor R5 is connected with the negative electrode of a power supply, the collector of the triode Q1 is connected with the other end of the resistor R4, the anode of the diode D4, the anode of the diode D2 and one end of the resistor R6 in parallel, the other end of the resistor R6 is connected with the emitter of the triode Q3, the base of the triode Q3 is in an off state, the cathode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the collector of the triode Q2, the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip in parallel, the cathode of the diode D2 is connected with the base of the triode Q2, the emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the negative electrode of the power supply.
In a second embodiment, the first memory chip 1 is a BG0 area bad defect address memory chip, the second memory chip 2 is a BG0 area bad defect address memory chip, the partition driving unit 3 includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D3, a diode D4, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel with one end of the resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 is connected in parallel with an anode of the diode D3, a base of the transistor Q1, and a cathode of the diode D1, an anode of the diode D1 is connected in parallel with one end of the resistor R4 and an anode of the power supply, and an emitter of the transistor Q1 is connected with an emitter of the resistor 46r 5, the other end of the resistor R5 is connected with the negative electrode of a power supply, the collector of the triode Q1 is connected with the other end of the resistor R4, the anode of the diode D4, the anode of the diode D2 and one end of the resistor R6 in parallel, the other end of the resistor R6 is connected with the emitter of the triode Q3, the cathode of the diode D3 is connected with the base of the triode Q3, the cathode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the collector of the triode Q2, the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip in parallel, the cathode of the diode D2 is connected with the base of the triode Q2, the emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the negative electrode of the power supply.
In a third embodiment, the first memory chip 1 is a BG1 area bad defect address memory chip, the second memory chip 2 is a BG1 area bad defect address memory chip, the partition driving unit 3 includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D2, a diode D4, a diode D3, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel to one end of a resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 and an anode of the diode D3 are in an off state, one end of the resistor R4 is connected to an anode of a power supply, a base of the transistor Q1 is in an off state, an emitter of the transistor Q1 is connected to one end of the resistor R5, and a cathode of the resistor R5 is connected to a cathode of the power supply, the collector of the triode Q1 is connected in parallel with the other end of the resistor R4, the anode of the diode D4, the anode of the diode D2 and one end of the resistor R6, the other end of the resistor R6 is connected with the emitter of the triode Q3, the base of the triode Q3 is connected with the cathode of the diode D3, the cathode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected in parallel with the collector of the triode Q2, the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip, the cathode of the diode D2 is connected with the base of the transistor Q2, the emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the cathode of the power supply.
In a fourth embodiment, the first memory chip 1 is a BG0 area bad defect address memory chip, the second memory chip 2 is a BG0 area bad defect address memory chip, the partition driving unit 3 includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D3, a diode D4, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel to one end of the resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 and an anode of the diode D3 are in an off state, one end of the resistor R4 is connected to an anode of a power supply, an emitter of the transistor Q1 is connected to one end of the resistor R5, the other end of the resistor R5 is connected to a cathode of the power supply, and the other end of the transistor Q1 is connected in parallel to a collector of the resistor R4, The diode comprises a diode D4 and one end of a resistor R6, the other end of the resistor R6 is connected with an emitter of the triode Q3, the cathode of the diode D3 is connected with a base of the triode Q3, the cathode of the diode D4 is connected with one end of a resistor R2, the other end of the resistor R2 is connected with a collector of the triode Q2, a BG1 terminal of a first memory chip and a BG1 terminal of a second memory chip in parallel, the base of the triode Q2 is in an off state, the emitter of the triode Q2 is connected with one end of a resistor R3, and the other end of the resistor R3 is connected with the cathode of a power supply.
Fig. 2 is a block diagram of a memory module selected from the inside of the chip under a good condition, and referring to fig. 2, a BG 1-0 region inside the memory chip is set as a BG0 region, i.e., the upper half; the BG 1-1 region inside the memory chip is set as a BG1 region, which is the lower half.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. The utility model provides a novel divide bit memory module from top to bottom which characterized in that, memory module includes: the memory chip module and the partition driving unit are connected to the circuit board;
the memory chip module comprises eight or sixteen memory chip units, each memory chip unit comprises a first memory chip and a second memory chip, the first memory chip and/or the second memory chip are memory chips with bad defect addresses, the first memory chip and the second memory chip are both provided with BG0 terminals and BG1 terminals, and the first memory chip and the second memory chip are both provided with BG0 regions and BG1 regions; the first memory chip and the second memory chip are both DDR4 memory chips;
the input end of the partition driving unit is provided with two terminals, the first input end of the partition driving unit is connected with the positive electrode of a power supply on the circuit board, the second input end of the partition driving unit is connected with the negative electrode of the power supply on the circuit board, the output end of the partition driving unit is provided with two terminals, the first output end of the partition driving unit is connected with the BG0 terminal of the first memory chip and the BG0 terminal of the second memory chip in parallel and used for providing high level or low level for the BG0 terminal of the first memory chip and the BG0 terminal of the second memory chip; the second output end of the partition driving unit is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, and is used for providing a high level or a low level for a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip.
2. The novel upper and lower bit-splitting memory module as claimed in claim 1, wherein the first memory chip is a BG1 area bad defect address memory chip, and the second memory chip is a BG1 area bad defect address memory chip, the partition driving unit comprises a partition driving circuit, the partition driving circuit comprises a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D4, a transistor Q1, a transistor Q2 and a transistor Q3, a collector of the transistor Q3 is connected in parallel with one end of a resistor R1, a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, the other end of the resistor R1 is connected in parallel with a base of the transistor Q1 and a cathode of a diode D1, an anode of the diode D1 is connected in parallel with one end of the resistor R4 and an anode of a power supply, an emitter of the triode Q1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a negative electrode of a power supply, a collector of the triode Q1 is connected with the other end of the resistor R4, an anode of a diode D4, an anode of a diode D2 and one end of a resistor R6 in parallel, the other end of the resistor R6 is connected with an emitter of the triode Q3, a base of the triode Q3 is in an off state, a negative electrode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with a collector of the triode Q2, a BG1 terminal of a first memory chip and a BG1 terminal of a second memory chip in parallel, a negative electrode of the diode D2 is connected with a base of the triode Q2, an emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a negative electrode of the power supply.
3. The novel upper and lower bit-splitting memory module as claimed in claim 1, wherein the first memory chip is a BG0 area bad defect address memory chip, and the second memory chip is a BG0 area bad defect address memory chip, the partition driving unit includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D1, a diode D2, a diode D3, a diode D4, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel with one end of a resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 is connected in parallel with an anode of the diode D3, a base of the transistor Q1, and a cathode of the diode D1, an anode of the diode D1 is connected in parallel with one end of the resistor R4 and an anode of the diode D3634, an emitter of the triode Q1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a negative electrode of a power supply, a collector of the triode Q1 is connected with the other end of the resistor R4, a positive electrode of a diode D4, a positive electrode of a diode D2 and one end of a resistor R6 in parallel, the other end of the resistor R6 is connected with an emitter of the triode Q3, a negative electrode of the diode D3 is connected with a base of the triode Q3, a negative electrode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with a collector of the triode Q2, a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip in parallel, a negative electrode of the diode D2 is connected with a base of the triode Q2, an emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a negative electrode of the power supply.
4. The novel upper and lower bit-splitting memory module as claimed in claim 1, wherein the first memory chip is a BG1 area bad defect address memory chip, and the second memory chip is a BG1 area bad defect address memory chip, the partition driving unit includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D2, a diode D4, a diode D3, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel with one end of a resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 and the anode of the diode D3 are in an off state, one end of the resistor R4 is connected to the anode of a power supply, a base of the transistor Q1 is in an off state, an emitter of the triode Q1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a negative electrode of a power supply, a collector of the triode Q1 is connected with the other end of the resistor R4, a positive electrode of a diode D4, a positive electrode of a diode D2 and one end of a resistor R6 in parallel, the other end of the resistor R6 is connected with an emitter of the triode Q3, a base of the triode Q3 is connected with a negative electrode of the diode D3, a negative electrode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with a collector of the triode Q2, a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip in parallel, a negative electrode of the diode D2 is connected with a base of the triode Q2, an emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with a negative electrode of the power supply.
5. The novel upper and lower bit-splitting memory module as claimed in claim 1, wherein the first memory chip is a BG0 area bad defect address memory chip, and the second memory chip is a BG0 area bad defect address memory chip, the partition driving unit includes a partition driving circuit, the partition driving circuit includes a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D3, a diode D4, a transistor Q1, a transistor Q2, and a transistor Q3, a collector of the transistor Q3 is connected in parallel with one end of the resistor R1, a BG0 terminal of the first memory chip, and a BG0 terminal of the second memory chip, the other end of the resistor R1 and the anode of the diode D3 are in an off state, one end of the resistor R4 is connected to the anode of a power supply, an emitter of the transistor Q1 is connected to one end of the resistor R5, the other end of the resistor R5 is connected with the negative electrode of a power supply, the collector of the triode Q1 is connected with the other end of the resistor R4, the positive electrode of the diode D4 and one end of the resistor R6 in parallel, the other end of the resistor R6 is connected with the emitter of the triode Q3, the negative electrode of the diode D3 is connected with the base of the triode Q3, the negative electrode of the diode D4 is connected with one end of the resistor R2, the other end of the resistor R2 is connected with the collector of the triode Q2, the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip in parallel, the base of the triode Q2 is in an off state, the emitter of the triode Q2 is connected with one end of the resistor R3, and the other end of the resistor R3 is connected with the negative electrode of the power supply.
6. The novel split-bit memory module as claimed in claim 1, wherein the first and second memory chips are both DDR4 memory chips.
7. The memory module as claimed in claim 1, wherein the circuit board is a PCB.
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