CN215494791U - Spliced memory module - Google Patents
Spliced memory module Download PDFInfo
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- CN215494791U CN215494791U CN202121702191.8U CN202121702191U CN215494791U CN 215494791 U CN215494791 U CN 215494791U CN 202121702191 U CN202121702191 U CN 202121702191U CN 215494791 U CN215494791 U CN 215494791U
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- memory chip
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Abstract
The utility model discloses a spliced memory module, which comprises: the device comprises a memory chip module, a shunt enabling unit and a circuit board, wherein the memory chip module and the shunt enabling unit are connected to the circuit board; the input end of the shunt enabling unit is connected with a power supply on the circuit board, the output end of the shunt enabling unit is provided with two terminals, the first output end of the shunt enabling unit is connected with a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip in parallel, the second output end of the shunt enabling unit is connected with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip in parallel, the shunt enabling unit is used for providing high level or low level of a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, or the shunt enabling unit is used for providing high level or low level of a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip. By means of the circuit splicing technology, the memory chip is fully utilized, and cost is reduced.
Description
Technical Field
The utility model relates to the technical field of memory chip modules, in particular to a spliced memory module.
Background
With the rapid development of electronic products, many electronic products need to be applied to a memory chip to store data information. The memory module is reasonably arranged on the PCB so as to achieve the function of storing data of the memory module. At present, in the production test process of the memory module, a part of bad chips can inevitably occur, the bad chips can have a bad defect address range, and the bad chips can not realize all functions due to certain defects, and are often discarded, so that the waste of the chips is caused. If the memory chips can be used, the cost of the memory module can be reduced.
Therefore, in view of the above problems, the conventional chip module needs to be further improved to reuse the defective memory chip.
SUMMERY OF THE UTILITY MODEL
The utility model aims to solve the problem of waste of bad chips, and the memory chips with bad defect address ranges in the normal test process are reasonably arranged on a circuit board after being recombined through the splicing circuit technology of a first memory chip and a second memory chip so as to obtain a spliced memory module; specifically, a BG0 terminal or a BG1 terminal of a bad memory chip is adopted to connect the output end of the shunt enabling unit, and the shunt enabling unit can provide a BG0 terminal or a BG1 terminal of the memory chip with high level or low level to realize the combination of the memory chips; the BG0 terminal of the first memory chip is connected with the BG0 terminal of the second memory chip, or the BG1 terminal of the first memory chip is connected with the BG1 terminal of the second memory chip, and then the high level or the low level is output through the routing enabling unit, so that the combination of the memory chips can be effectively realized, and the bad memory chips can be reused.
The technical scheme of the utility model is as follows:
a tiled memory module, the memory module comprising: the device comprises a memory chip module, a shunt enabling unit and a circuit board, wherein the memory chip module and the shunt enabling unit are connected to the circuit board;
the memory chip module comprises eight or sixteen memory chip units, each memory chip unit comprises a first memory chip and a second memory chip, the first memory chip and/or the second memory chip are memory chips with bad defect addresses, the first memory chip and the second memory chip are both provided with BG0 terminals and BG1 terminals, the first memory chip and the second memory chip are both provided with a BG0 region and a BG1 region, the input end of the shunt enabling unit is provided with two terminals, the first input end of the shunt enabling unit is connected with the positive pole of a power supply on the circuit board, the second input end of the shunt enabling unit is connected with the negative pole of the power supply on the circuit board, the output end of the shunt enabling unit is provided with two terminals, the first output end of the shunt enabling unit is connected with the BG0 terminal of the first memory chip and the BG0 terminal of the second memory chip in parallel, the second output end of the shunt enabling unit is connected with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip in parallel, the shunt enabling unit is used for providing a high level or a low level of a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, or the shunt enabling unit is used for providing a high level or a low level of a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip.
Further, the first memory chip is a BG0 memory chip with bad defect address, and the second memory chip is a BG0 memory chip with bad defect address, the shunt enable unit comprises a shunt enable circuit, the shunt enabling circuit comprises a resistor R3, a resistor R4, a resistor R6, a diode D1 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R6, the other end of the resistor R4 is connected in parallel with the anode of the power supply and the anode of the diode D1, the cathode of the diode D1 is connected with the base of the triode Q1, the emitter of the triode is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the negative electrode of the power supply, the other end of the resistor R6 is connected with the BG0 terminal of the first memory chip and the BG0 terminal of the second memory chip in parallel, and the second output end of the shunt enabling unit is in a disconnected state.
Further, the first memory chip is a memory chip with a BG1 area bad defect address, the second memory chip is a memory chip with a BG1 area bad defect address, the shunt enabling unit includes a shunt enabling circuit, the shunt enabling circuit includes a resistor R3, a resistor R4, a resistor R6 and a triode Q1, a collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R6, the other end of the resistor R4 is connected with an anode of the power supply, a base of the triode Q1 is in an off state, an emitter of the triode is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R6 is connected in parallel with a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, and a second shunt output end of the shunt enabling unit is in an off state.
Further, the first memory chip is a BG1 memory chip with bad defect address, and the second memory chip is a BG1 memory chip with bad defect address, the shunt enable unit comprises a shunt enable circuit, the shunt enabling circuit comprises a resistor R3, a resistor R4, a resistor R5, a diode D1 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with the anode of the power supply and the anode of the diode D1, the cathode of the diode D1 is connected with the base of the triode Q1, the emitter of the triode is connected with one end of the resistor R3, the other end of the resistor R3 is connected with the negative electrode of the power supply, the other end of the resistor R5 is connected with the BG1 terminal of the first memory chip and the BG1 terminal of the second memory chip in parallel, and the first output end of the shunt enabling unit is in a disconnected state.
Further, the first memory chip is a memory chip with a BG0 area bad defect address, the second memory chip is a memory chip with a BG0 area bad defect address, the shunt enabling unit includes a shunt enabling circuit, the shunt enabling circuit includes a resistor R3, a resistor R4, a resistor R5 and a triode Q1, a collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected with an anode of the power supply, a base of the triode Q1 is in an off state, an emitter of the triode is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, and a first shunt output end of the shunt enabling unit is in an off state.
With the arrangement, by using the diode D1, whether the base of the transistor Q1 is turned on or not can be realized through the diode D1, and for realizing the purpose of disconnecting the base of the transistor Q1, the diode D1 is subjected to blow-out processing or directly taken out processing. By adopting the shunt enabling unit, the single-channel work can be realized by only the resistor R5 or only the resistor R6, the high level or the low level of the BGO terminal of the memory chip or the BG1 terminal of the memory chip is driven, and the simple and convenient fixed circuit splicing is realized.
Further, the first memory chip is a good memory chip or a bad memory chip, and the second memory chip is a good memory chip or a bad memory chip.
Further, the first memory chip and the second memory chip are both DDR4 memory chips.
Further, the circuit board is a PCB circuit board.
Advantageous effects
According to the utility model, by adopting the splicing circuit technology of the first memory chip and the second memory chip, after the bad memory chips are recombined, the memory chips are reasonably arranged on the circuit board, and a spliced memory module can be obtained; specifically, a BG0 terminal or a BG1 terminal of a bad memory chip is adopted to connect the output end of the shunt enabling unit, and the shunt enabling unit can provide a BG0 terminal or a BG1 terminal of the memory chip with high level or low level to realize the combination of the memory chips; the BG0 terminal of the first memory chip is connected with the BG0 terminal of the second memory chip, or the BG1 terminal of the first memory chip is connected with the BG1 terminal of the second memory chip, and then the high level or the low level is output through the routing enabling unit, so that the combination of the memory chips can be effectively realized, and the bad memory chips can be reused. The diode is switched on and off, so that the triode can be driven to be switched on and off, and the high level or the low level of the memory chip is provided; the driving under a fixed circuit can be realized by adopting a shunt enabling unit with a triode and a resistor.
Drawings
Fig. 1 is a schematic structural diagram of a tiled memory module according to the present invention.
Fig. 2 is a block diagram illustrating internal selection of a memory chip of a tiled memory module according to the present invention.
Reference numerals: 1. a first memory chip; 2. a second memory chip; 3. a shunt enable unit.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
Referring to fig. 1, the present invention provides a tiled memory module, which includes: the device comprises a memory chip module, a shunt enabling unit and a circuit board, wherein the memory chip module and the shunt enabling unit are connected to the circuit board;
the memory chip module comprises eight or sixteen memory chip units, each memory chip unit comprises a first memory chip 1 and a second memory chip 2, each memory chip 1 and/or each memory chip 2 is a memory chip with a bad defect address, each memory chip is provided with a BG0 terminal and a BG1 terminal, each memory chip is provided with a BG0 region and a BG1 region, the input end of the shunt enabling unit 3 is provided with two terminals, the first input end of the shunt enabling unit is connected with the positive pole of a power supply on the circuit board, the second input end of the shunt enabling unit is connected with the negative pole of the power supply on the circuit board, the output end of the shunt enabling unit is provided with two terminals, the first output end of the enabling unit is connected with the BG0 terminal of the first memory chip and the BG0 terminal of the second memory chip in parallel, the second output end of the shunt enabling unit is connected with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip in parallel, the shunt enabling unit is used for providing a high level or a low level of a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, or the shunt enabling unit is used for providing a high level or a low level of a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip.
In the first embodiment, the first memory chip 1 is a BG0 area bad defect address memory chip, the second memory chip 2 is a BG0 area bad defect address memory chip, the shunt enabling unit 3 includes a shunt enabling circuit, the shunt enabling circuit includes a resistor R3, a resistor R4, a resistor R6, a diode D1, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R6, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D1, a cathode of the diode D1 is connected with a base of the transistor Q1, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, and the other end of the resistor R6 is connected in parallel with a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, the second output end of the shunt enabling unit is in an off state.
In a second embodiment, the first memory chip 1 is a memory chip with a BG1 area defective address, the second memory chip 2 is a memory chip with a BG1 area defective address, the shunt enabling unit 3 includes a shunt enabling circuit, the shunt enabling circuit includes a resistor R3, a resistor R4, a resistor R6, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R6, the other end of the resistor R4 is connected to an anode of the power supply, a base of the transistor Q1 is in an off state, an emitter of the transistor is connected to one end of the resistor R3, the other end of the resistor R3 is connected to a cathode of the power supply, the other end of the resistor R6 is connected in parallel with a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, and a second output end of the shunt enabling unit is in an off state.
In a third embodiment, the first memory chip 1 is a BG1 area bad defect address memory chip, the second memory chip 2 is a BG1 area bad defect address memory chip, the shunt enabling unit 3 includes a shunt enabling circuit, the shunt enabling circuit includes a resistor R3, a resistor R4, a resistor R5, a diode D1, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D1, a cathode of the diode D1 is connected with a base of the transistor Q1, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, and the other end of the resistor R5 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, the first output end of the shunt enabling unit is in an off state.
In a fourth embodiment, the first memory chip 1 is a memory chip with a BG0 area defective address, the second memory chip 2 is a memory chip with a BG0 area defective address, the shunt enabling unit 3 includes a shunt enabling circuit, the shunt enabling circuit includes a resistor R3, a resistor R4, a resistor R5, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected to an anode of the power supply, a base of the transistor Q1 is in an off state, an emitter of the transistor is connected to one end of the resistor R3, the other end of the resistor R3 is connected to a cathode of the power supply, the other end of the resistor R5 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, and a first output end of the shunt enabling unit is in an off state.
The first memory chip 1 and the second memory chip 2 are both DDR4 memory chips. The circuit board is a PCB circuit board.
Fig. 2 is a block diagram showing an internal selection of the memory module, and referring to fig. 2, a BG 1-0 region in the memory chip is a BG0 region, and a BG 1-1 region in the memory chip is a BG1 region.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the utility model, the scope of which is defined in the appended claims and their equivalents.
Claims (7)
1. The spliced memory module is characterized by comprising: the device comprises a memory chip module, a shunt enabling unit and a circuit board, wherein the memory chip module and the shunt enabling unit are connected to the circuit board;
the memory chip module comprises eight or sixteen memory chip units, each memory chip unit comprises a first memory chip and a second memory chip, the first memory chip and/or the second memory chip are memory chips with bad defect addresses, the first memory chip and the second memory chip are both provided with BG0 terminals and BG1 terminals, the first memory chip and the second memory chip are both provided with a BG0 region and a BG1 region, the input end of the shunt enabling unit is provided with two terminals, the first input end of the shunt enabling unit is connected with the positive pole of a power supply on the circuit board, the second input end of the shunt enabling unit is connected with the negative pole of the power supply on the circuit board, the output end of the shunt enabling unit is provided with two terminals, the first output end of the shunt enabling unit is connected with the BG0 terminal of the first memory chip and the BG0 terminal of the second memory chip in parallel, the second output end of the shunt enabling unit is connected with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip in parallel, the shunt enabling unit is used for providing a high level or a low level of a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, or the shunt enabling unit is used for providing a high level or a low level of a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip.
2. The tiled memory module of claim 1, wherein the first memory chip is a BG0 bad defect address memory chip, the second memory chip is a BG0 bad defect address memory chip, the shunt enable unit comprises a shunt enable circuit, the shunt enable circuit comprises a resistor R3, a resistor R4, a resistor R6, a diode D1 and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R6, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D1, a cathode of the diode D1 is connected with a base of the transistor Q1, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R6 is connected in parallel with a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, the second output end of the shunt enabling unit is in an off state.
3. The tiled memory module of claim 1, wherein the first memory chip is a BG1 area bad defect address memory chip, and the second memory chip is a BG1 memory chip with bad defect address, the shunt enable unit comprises a shunt enable circuit, the shunt enabling circuit comprises a resistor R3, a resistor R4, a resistor R6 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R6, the other end of the resistor R4 is connected with the anode of the power supply, the base of the triode Q1 is in an off state, the emitter of the triode is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the negative electrode of a power supply, the other end of the resistor R6 is connected in parallel with a BG0 terminal of the first memory chip and a BG0 terminal of the second memory chip, and the second output end of the shunt enabling unit is in an off state.
4. The tiled memory module of claim 1, wherein the first memory chip is a BG1 bad defect address memory chip, the second memory chip is a BG1 bad defect address memory chip, the shunt enable unit comprises a shunt enable circuit, the shunt enable circuit comprises a resistor R3, a resistor R4, a resistor R5, a diode D1 and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D1, a cathode of the diode D1 is connected with a base of the transistor Q1, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, the first output end of the shunt enabling unit is in an off state.
5. The tiled memory module of claim 1, wherein the first memory chip is a BG0 area bad defect address memory chip, and the second memory chip is a BG0 memory chip with bad defect address, the shunt enable unit comprises a shunt enable circuit, the shunt enabling circuit comprises a resistor R3, a resistor R4, a resistor R5 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected with the anode of the power supply, the base of the triode Q1 is in an off state, the emitter of the triode is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the negative electrode of a power supply, the other end of the resistor R5 is connected in parallel with a BG1 terminal of the first memory chip and a BG1 terminal of the second memory chip, and the first output end of the shunt enabling unit is in an off state.
6. The tiled memory module of claim 1, wherein the first memory chip and the second memory chip are both DDR4 memory chips.
7. The tiled memory module of claim 1, wherein the circuit board is a PCB circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121702191.8U CN215494791U (en) | 2021-07-26 | 2021-07-26 | Spliced memory module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121702191.8U CN215494791U (en) | 2021-07-26 | 2021-07-26 | Spliced memory module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN215494791U true CN215494791U (en) | 2022-01-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202121702191.8U Active CN215494791U (en) | 2021-07-26 | 2021-07-26 | Spliced memory module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN215494791U (en) |
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2021
- 2021-07-26 CN CN202121702191.8U patent/CN215494791U/en active Active
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