CN215265584U - Novel control branch position memory module - Google Patents
Novel control branch position memory module Download PDFInfo
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- CN215265584U CN215265584U CN202121432550.2U CN202121432550U CN215265584U CN 215265584 U CN215265584 U CN 215265584U CN 202121432550 U CN202121432550 U CN 202121432550U CN 215265584 U CN215265584 U CN 215265584U
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Abstract
The utility model discloses a novel control and divide position memory module, it includes: the memory chip module and the enabling unit are connected to the circuit board; the memory chip module is eight or sixteen memory chip units, each memory chip unit comprises a first memory chip and a second memory chip, the input end of the enabling unit is connected with a power supply on the circuit board, the first output end of the enabling unit is connected with the A17 terminal of the first memory chip and the A17 terminal of the second memory chip in parallel, the second output end of the enabling unit is connected with the A16 terminal of the first memory chip and the A16 terminal of the second memory chip in parallel, the third output end of the enabling unit is connected with the A15 terminal of the first memory chip and the A15 terminal of the second memory chip in parallel, and the enabling unit is used for providing high level or low level of the first memory chip and the second memory chip. The memory chips are spliced by the splicing circuit technology, bad memory chips are reused, and cost is low.
Description
Technical Field
The utility model relates to a memory chip module technical field, concretely relates to novel control reposition of redundant personnel memory module.
Background
With the rapid development of electronic products, many electronic products need to be applied to a memory chip to store data information. The memory module is reasonably arranged on the PCB so as to achieve the function of storing data of the memory module. At present, in the production test process of the memory module, a part of bad chips can inevitably occur, the bad chips can have a bad defect address range, and the bad chips can not realize all functions due to certain defects, and are often discarded, so that the waste of the chips is caused. If the address terminals of the chips are recombined and utilized, the cost of the memory module can be reduced.
Therefore, in view of the above problems, the conventional chip module needs to be further improved to reuse the defective memory chip.
SUMMERY OF THE UTILITY MODEL
The purpose of the utility model is to overcome the waste problem of bad chips, to the memory chip of bad defect address range appearing in the normal test process, through the concatenation circuit technology of memory chip, after recombining bad memory chip, rationally arrange on the circuit board, can obtain the memory module after the concatenation; specifically, the memory chip with bad performance is connected with the enabling unit, the enabling unit can provide high level or low level required by work for the memory chip, and the memory chip can be spliced; the A17 terminal of the first memory chip is connected with the A17 terminal of the second memory chip, or the A16 terminal of the first memory chip is connected with the A16 terminal of the second memory chip, or the A15 terminal of the first memory chip is connected with the A15 terminal of the second memory chip, and then the enabling unit provides high level or low level for the combined memory module, so that the splicing of bad memory chips can be effectively realized, and the bad memory chips are reused.
The technical scheme of the utility model is specifically as follows:
the utility model provides a novel control and divide position memory module, memory module includes: the device comprises a memory chip module, an enabling unit and a circuit board, wherein the memory chip module and the enabling unit are connected to the circuit board;
the memory chip module comprises eight or sixteen memory chip units, each memory chip unit comprises a first memory chip and a second memory chip, the first memory chip and/or the second memory chip are memory chips with bad defect addresses, the first memory chip and the second memory chip are respectively provided with an A15 terminal, an A16 terminal and an A17 terminal, the first memory chip and the second memory chip are respectively provided with a left half part and a right half part, the input end of the enabling unit is provided with two terminals, the first input end of the enabling unit is connected with the positive pole of a power supply on the circuit board, the second input end of the enabling unit is connected with the negative pole of the power supply on the circuit board, the output end of the enabling unit is provided with three terminals, and the first output end of the enabling unit is connected with the A17 terminal of the first memory chip and the A17 terminal of the second memory chip in parallel, the second output end of the enable unit is connected in parallel with an a16 terminal of the first memory chip and an a16 terminal of the second memory chip, the third output end of the enable unit is connected in parallel with an a15 terminal of the first memory chip and an a15 terminal of the second memory chip, the enable unit is used for providing a high level or a low level of the a17 terminal of the first memory chip and the a17 terminal of the second memory chip, or the enable unit is used for providing a high level or a low level of the a16 terminal of the first memory chip and the a16 terminal of the second memory chip, or the enable unit is used for providing a high level or a low level of the a15 terminal of the first memory chip and the a15 terminal of the second memory chip.
Further, at least one memory chip with a poor right half of the first memory chip and the second memory chip includes an enabling circuit, the enabling circuit includes a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D3, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D3, a cathode of the diode D3 is connected with a base of the transistor Q1, an emitter of the transistor Q1 is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected with one end of the resistor R6, and the other end of the resistor R6 is connected in parallel with an a17 terminal of the first memory chip and an a17 terminal of the second memory chip, and the second output end and the third output end of the enabling unit are both in an off state.
Further, at least one memory chip with a poor right half of the first memory chip and the second memory chip includes an enabling circuit, the enabling circuit includes a resistor R3, a resistor R4, a resistor R5, a resistor R7, a diode D3, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D3, a cathode of the diode D3 is connected with a base of the transistor Q1, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected with one end of the resistor R7, and the other end of the resistor R7 is connected in parallel with an a16 terminal of the first memory chip and an a16 terminal of the second memory chip, the first output end and the third output end of the enabling unit are both in an off state.
Further, at least one memory chip with a poor right half of the first memory chip and the second memory chip includes an enabling circuit, the enabling circuit includes a resistor R3, a resistor R4, a resistor R5, a resistor R8, a diode D3, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D3, a cathode of the diode D3 is connected with a base of the transistor Q1, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected with one end of the resistor R8, and the other end of the resistor R8 is connected in parallel with an a15 terminal of the first memory chip and an a15 terminal of the second memory chip, the first output end and the second output end of the enabling unit are both in an off state.
Further, at least one memory chip with poor left half part in the first memory chip and the second memory chip, the enabling unit comprises an enabling circuit which comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected with the anode of the power supply, the base of the triode Q1 is in an off state, the emitter of the triode is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the negative electrode of a power supply, the other end of the resistor R5 is connected with one end of the resistor R6, the other end of the resistor R6 is connected with the A17 terminal of the first memory chip and the A17 terminal of the second memory chip in parallel, and the second output end and the third output end of the enabling unit are both in an off state.
Further, at least one memory chip with poor left half part in the first memory chip and the second memory chip, the enabling unit comprises an enabling circuit which comprises a resistor R3, a resistor R4, a resistor R5, a resistor R7 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with the anode of the power supply, the base of the triode Q1 is in an off state, the emitter of the triode is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the negative electrode of a power supply, the other end of the resistor R5 is connected with one end of the resistor R7, the other end of the resistor R7 is connected with the A16 terminal of the first memory chip and the A16 terminal of the second memory chip in parallel, and the first output end and the third output end of the enabling unit are both in an off state.
Further, at least one memory chip with poor left half part in the first memory chip and the second memory chip, the enabling unit comprises an enabling circuit which comprises a resistor R3, a resistor R4, a resistor R5, a resistor R8 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with the anode of the power supply, the base of the triode Q1 is in an off state, the emitter of the triode is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the negative electrode of a power supply, the other end of the resistor R5 is connected with one end of the resistor R8, the other end of the resistor R8 is connected with the A15 terminal of the first memory chip and the A15 terminal of the second memory chip in parallel, and the first output end and the second output end of the enabling unit are both in an off state.
By adopting the diode, whether the base electrode of the triode is conducted or not can be realized through the diode, and the diode is burnt out or directly taken out for processing for realizing disconnection of the base electrode of the triode. By adopting the enabling unit and combining with the existence of the resistor R6 or the resistor R7 or the resistor R8, the single-path operation can be realized to drive the high level or the low level of the memory chip.
Further, the first memory chip is a good memory chip or a bad memory chip, and the second memory chip is a good memory chip or a bad memory chip.
Further, the first memory chip and the second memory chip are both DDR4 memory chips.
Further, the circuit board is a PCB circuit board.
Advantageous effects
The utility model discloses a concatenation circuit technology of memory chip, after recombining bad memory chip, rationally arrange on the circuit board, can obtain the memory module after the concatenation; specifically, the memory chip with bad performance is connected with the enabling unit, the enabling unit can provide high level or low level required by work for the memory chip, and the memory chip can be spliced; the A17 terminal of the first memory chip is connected with the A17 terminal of the second memory chip, or the A16 terminal of the first memory chip is connected with the A16 terminal of the second memory chip, or the A15 terminal of the first memory chip is connected with the A15 terminal of the second memory chip, and then the enabling unit provides high level or low level for the combined memory module, so that the splicing of bad memory chips can be effectively realized, and the bad memory chips are reused. The diode is switched on or off, so that the triode can be driven to be switched on or off, and high level or low level required by the memory chip is further realized; the driving of the fixed circuit can be realized by using an enabling unit with a diode, a triode and a resistor.
Drawings
Fig. 1 is a schematic structural view of a left-right separate internal memory module according to the present invention.
Fig. 2 is a block diagram illustrating internal selection of memory chips of the left-right split-bit memory module according to the present invention.
Reference numerals: 1. a first memory chip; 2. a second memory chip; 3. the unit is enabled.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work all belong to the protection scope of the present invention.
Referring to fig. 1, the utility model provides a pair of novel control and divide position memory module, the memory module includes: the device comprises a memory chip module, an enabling unit and a circuit board, wherein the memory chip module and the enabling unit are connected to the circuit board;
the memory chip module comprises eight or sixteen memory chip units, each memory chip unit comprises a first memory chip 1 and a second memory chip 2, each first memory chip 1 and/or each second memory chip 2 is a memory chip with a bad defect address, each first memory chip and each second memory chip are respectively provided with an A15 terminal, an A16 terminal and an A17 terminal, each first memory chip and each second memory chip are respectively provided with a left half part and a right half part, the input end of the enabling unit 3 is provided with two terminals, the first input end of the enabling unit is connected with the positive pole of a power supply on the circuit board, the second input end of the enabling unit is connected with the negative pole of the power supply on the circuit board, the output end of the enabling unit is provided with three terminals, and the first output end of the enabling unit is connected with the A17 terminal of the first memory chip and the A17 terminal of the second memory chip in parallel, the second output end of the enable unit is connected in parallel with an a16 terminal of the first memory chip and an a16 terminal of the second memory chip, the third output end of the enable unit is connected in parallel with an a15 terminal of the first memory chip and an a15 terminal of the second memory chip, the enable unit is used for providing a high level or a low level of the a17 terminal of the first memory chip and the a17 terminal of the second memory chip, or the enable unit is used for providing a high level or a low level of the a16 terminal of the first memory chip and the a16 terminal of the second memory chip, or the enable unit is used for providing a high level or a low level of the a15 terminal of the first memory chip and the a15 terminal of the second memory chip.
In a first embodiment, the enable unit 3 includes an enable circuit, the enable circuit includes a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D3, and a transistor Q1, a collector of the transistor Q1 is connected in parallel to one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel to an anode of the power supply and an anode of the diode D3, a cathode of the diode D3 is connected to a base of the transistor Q1, an emitter of the transistor Q1 is connected to one end of the resistor R3, the other end of the resistor R3 is connected to a cathode of the power supply, the other end of the resistor R5 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected in parallel to an a17 terminal of the first memory chip and an a17 terminal of the second memory chip, and the second output end and the third output end of the enabling unit are both in an off state.
In a second embodiment, the enable unit includes an enable circuit, the enable circuit includes a resistor R3, a resistor R4, a resistor R5, a resistor R7, a diode D3, and a transistor Q1, a collector of the transistor Q1 is connected in parallel to one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel to an anode of the power supply and an anode of the diode D3, a cathode of the diode D3 is connected to a base of the transistor Q1, an emitter of the transistor is connected to one end of the resistor R3, the other end of the resistor R3 is connected to a cathode of the power supply, the other end of the resistor R5 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected in parallel to an a16 terminal of the first memory chip and an a16 terminal of the second memory chip, the first output end and the third output end of the enabling unit are both in an off state.
In a third embodiment, the enable unit 3 includes an enable circuit, the enable circuit includes a resistor R3, a resistor R4, a resistor R5, a resistor R8, a diode D3, and a transistor Q1, a collector of the transistor Q1 is connected in parallel to one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel to an anode of the power supply and an anode of the diode D3, a cathode of the diode D3 is connected to a base of the transistor Q1, an emitter of the transistor is connected to one end of the resistor R3, the other end of the resistor R3 is connected to a cathode of the power supply, the other end of the resistor R5 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected in parallel to an a15 terminal of the first memory chip and an a15 terminal of the second memory chip, the first output end and the second output end of the enabling unit are both in an off state.
In a fourth embodiment, at least one of the first memory chip 1 and the second memory chip 2 having a defective left half is a defective memory chip, the enabling unit 3 comprises an enabling circuit which comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected with the anode of the power supply, the base of the triode Q1 is in an off state, the emitter of the triode is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the negative electrode of a power supply, the other end of the resistor R5 is connected with one end of the resistor R6, the other end of the resistor R6 is connected with the A17 terminal of the first memory chip and the A17 terminal of the second memory chip in parallel, and the second output end and the third output end of the enabling unit are both in an off state.
In the fifth embodiment, at least one of the first memory chip 1 and the second memory chip 2 having a defective left half portion, the enabling unit 3 comprises an enabling circuit which comprises a resistor R3, a resistor R4, a resistor R5, a resistor R7 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with the anode of the power supply, the base of the triode Q1 is in an off state, the emitter of the triode is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the negative electrode of a power supply, the other end of the resistor R5 is connected with one end of the resistor R7, the other end of the resistor R7 is connected with the A16 terminal of the first memory chip and the A16 terminal of the second memory chip in parallel, and the first output end and the third output end of the enabling unit are both in an off state.
In a sixth embodiment, at least one of the first memory chip 1 and the second memory chip 2 having a defective left half is selected, the enabling unit 3 comprises an enabling circuit which comprises a resistor R3, a resistor R4, a resistor R5, a resistor R8 and a triode Q1, the collector of the triode Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with the anode of the power supply, the base of the triode Q1 is in an off state, the emitter of the triode is connected with one end of a resistor R3, the other end of the resistor R3 is connected with the negative electrode of a power supply, the other end of the resistor R5 is connected with one end of the resistor R8, the other end of the resistor R8 is connected with the A15 terminal of the first memory chip and the A15 terminal of the second memory chip in parallel, and the first output end and the second output end of the enabling unit are both in an off state.
The first memory chip 1 and the second memory chip 2 are both DDR4 memory chips.
Fig. 2 is a block diagram of the internal selection of the memory module under good conditions, and as shown in fig. 2, a region with the highest column address of 0 in the memory chip is set as the left half, and a region with the highest column address of 1 in the memory chip is set as the right half.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. The utility model provides a novel control and divide position memory module which characterized in that, memory module includes: the device comprises a memory chip module, an enabling unit and a circuit board, wherein the memory chip module and the enabling unit are connected to the circuit board;
the memory chip module comprises eight or sixteen memory chip units, each memory chip unit comprises a first memory chip and a second memory chip, the first memory chip and/or the second memory chip are memory chips with bad defect addresses, the first memory chip and the second memory chip are respectively provided with an A15 terminal, an A16 terminal and an A17 terminal, the first memory chip and the second memory chip are respectively provided with a left half part and a right half part, the input end of the enabling unit is provided with two terminals, the first input end of the enabling unit is connected with the positive pole of a power supply on the circuit board, the second input end of the enabling unit is connected with the negative pole of the power supply on the circuit board, the output end of the enabling unit is provided with three terminals, and the first output end of the enabling unit is connected with the A17 terminal of the first memory chip and the A17 terminal of the second memory chip in parallel, the second output end of the enable unit is connected in parallel with an a16 terminal of the first memory chip and an a16 terminal of the second memory chip, the third output end of the enable unit is connected in parallel with an a15 terminal of the first memory chip and an a15 terminal of the second memory chip, the enable unit is used for providing a high level or a low level of the a17 terminal of the first memory chip and the a17 terminal of the second memory chip, or the enable unit is used for providing a high level or a low level of the a16 terminal of the first memory chip and the a16 terminal of the second memory chip, or the enable unit is used for providing a high level or a low level of the a15 terminal of the first memory chip and the a15 terminal of the second memory chip.
2. The novel left-right-side-divided memory module as claimed in claim 1, wherein at least one of the first memory chip and the second memory chip having a poor right half portion comprises an enabling circuit, the enabling circuit comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, a diode D3 and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of a diode D3, a cathode of the diode D3 is connected with a base of the transistor Q1, an emitter of the transistor Q1 is connected with one end of a resistor R3, the other end of a resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected with one end of a resistor R6, and the other end of the resistor R6 is connected in parallel with a17 a terminal of the first memory chip and a terminal 17 of the second memory chip, and the second output end and the third output end of the enabling unit are both in an off state.
3. The novel left-right split-bit memory module as claimed in claim 1, wherein at least one of the first memory chip and the second memory chip has a defective right half, the enabling unit comprises an enabling circuit, the enabling circuit comprises a resistor R3, a resistor R4, a resistor R5, a resistor R7, a diode D3 and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D3, a cathode of the diode D3 is connected with a base of the transistor Q1, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected with one end of the resistor R7, and the other end of the resistor R7 is connected in parallel with an a16 a terminal of the first memory chip and a16 a terminal of the second memory chip, the first output end and the third output end of the enabling unit are both in an off state.
4. The novel left-right split-bit memory module as claimed in claim 1, wherein at least one of the first memory chip and the second memory chip has a defective right half, the enabling unit comprises an enabling circuit, the enabling circuit comprises a resistor R3, a resistor R4, a resistor R5, a resistor R8, a diode D3 and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of the resistor R4 and one end of the resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply and an anode of the diode D3, a cathode of the diode D3 is connected with a base of the transistor Q1, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected with one end of the resistor R8, and the other end of the resistor R8 is connected in parallel with an a15 a terminal of the first memory chip and a15 a terminal of the second memory chip, the first output end and the second output end of the enabling unit are both in an off state.
5. The novel left-right split-bit memory module as claimed in claim 1, wherein at least one of the first memory chip and the second memory chip has a defective left half, the enabling unit comprises an enabling circuit, the enabling circuit comprises a resistor R3, a resistor R4, a resistor R5, a resistor R6, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R4 is connected with a positive electrode of the power supply, a base of the transistor Q1 is in an off state, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a negative electrode of the power supply, the other end of the resistor R5 is connected with one end of the resistor R6, and the other end of the resistor R6 is connected in parallel with an a17 terminal of the first memory chip and an a17 terminal of the second memory chip, and the second output end and the third output end of the enabling unit are both in an off state.
6. The novel left-right split-bit memory module as claimed in claim 1, wherein at least one of the first memory chip and the second memory chip has a defective left half, the enabling unit comprises an enabling circuit, the enabling circuit comprises a resistor R3, a resistor R4, a resistor R5, a resistor R7, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply, a base of the transistor Q1 is in an off state, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected with one end of the resistor R7, and the other end of the resistor R7 is connected in parallel with an a16 terminal of the first memory chip and an a16 terminal of the second memory chip, the first output end and the third output end of the enabling unit are both in an off state.
7. The novel left-right split-bit memory module as claimed in claim 1, wherein at least one of the first memory chip and the second memory chip has a defective left half, the enabling unit comprises an enabling circuit, the enabling circuit comprises a resistor R3, a resistor R4, a resistor R5, a resistor R8, and a transistor Q1, a collector of the transistor Q1 is connected in parallel with one end of a resistor R4 and one end of a resistor R5, the other end of the resistor R4 is connected in parallel with an anode of the power supply, a base of the transistor Q1 is in an off state, an emitter of the transistor is connected with one end of the resistor R3, the other end of the resistor R3 is connected with a cathode of the power supply, the other end of the resistor R5 is connected with one end of the resistor R8, and the other end of the resistor R8 is connected in parallel with an a15 terminal of the first memory chip and an a15 terminal of the second memory chip, the first output end and the second output end of the enabling unit are both in an off state.
8. The novel left-right split-bit memory module as claimed in claim 1, wherein the first memory chip and the second memory chip are both DDR4 memory chips.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121432550.2U CN215265584U (en) | 2021-06-25 | 2021-06-25 | Novel control branch position memory module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202121432550.2U CN215265584U (en) | 2021-06-25 | 2021-06-25 | Novel control branch position memory module |
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| CN215265584U true CN215265584U (en) | 2021-12-21 |
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