CN113380314A - Memory repair test method and system - Google Patents
Memory repair test method and system Download PDFInfo
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- CN113380314A CN113380314A CN202110682992.0A CN202110682992A CN113380314A CN 113380314 A CN113380314 A CN 113380314A CN 202110682992 A CN202110682992 A CN 202110682992A CN 113380314 A CN113380314 A CN 113380314A
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- 230000015654 memory Effects 0.000 title claims abstract description 123
- 238000010998 test method Methods 0.000 title claims abstract description 21
- 238000012360 testing method Methods 0.000 claims abstract description 61
- 239000013598 vector Substances 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 15
- 238000007405 data analysis Methods 0.000 claims abstract description 9
- 238000004458 analytical method Methods 0.000 claims description 9
- 238000004590 computer program Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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Abstract
The invention discloses a memory repair test method and a system, wherein the method comprises the following steps: generating an information statistical record table; performing data analysis and address resolution on the memory to be tested through the test vector to obtain address information and data information of a failed storage unit in the memory; recording the address information and the corresponding data information of the failed storage unit into an information statistical record table; after all the test vectors are executed, repairing the failed storage unit in the memory according to the information recorded in the information statistical record table; by adopting the memory repair test method, in the process of testing the memory by adopting a plurality of sections of test vectors, the middle does not need to pause, and after all the test vectors are executed, all the failed memory units are repaired in a unified and orderly manner.
Description
Technical Field
The invention relates to the technical field of memory repair detection, in particular to a high-efficiency memory repair test method and system.
Background
The memory chip is tested before leaving the factory, and in the production test of the current mainstream memory, the chip can not realize the normal storage function because of the defect problem of internal units of some memories. In order to reduce the chip cost and improve the chip yield, a part of redundant memory cells are reserved for replacing the failed memory cells when the chip is designed, so that the failure repair is realized. In the testing process, in order to ensure the storage performance of the memory to be stable, the testing machine often runs various testing vectors, if FAIL information exists in a certain testing vector, according to the traditional method, the testing vector is run once, the testing machine stops to process the FAIL information in the memory once, and if a large number of vectors need to be tested, the cost of the required testing time is high, so that the testing efficiency is low.
Disclosure of Invention
The present invention is directed to a method and a system for testing memory repair, which can effectively improve the testing efficiency of a memory chip.
In order to achieve the above object, the present invention discloses a memory repair test method, which comprises the following steps:
generating an information statistic record table, wherein the data structure in the information statistic record table corresponds to the address information and the data information of the storage unit in the memory;
performing data analysis and address analysis on a memory to be tested through the test vector to obtain address information and data information of a failed storage unit in the memory;
recording the address information and the corresponding data information of the failed storage unit into the information statistical record table;
and after all the test vectors are executed, repairing the failed storage unit in the memory according to the information recorded in the information statistical record table.
Preferably, the data structure of the information statistics recording table includes X bits, Y bits, and Z bits, where the X bits and the Y bits respectively include a plurality of information bits corresponding to address information of storage units in a memory, and the Z bits include a plurality of information bits corresponding to data information in the storage units of the memory; when the information of the failure storage unit is recorded into the information statistics recording table, the information bits corresponding to the X-bit and the Y-bit are found in the information statistics recording table according to the address information of the failure storage unit, a failure mark is made, and the data information of the failure storage unit is recorded into the information bits in the Z-bit corresponding to the failure mark.
Preferably, the method for repairing the failed memory cell in the memory according to the information recorded in the information statistics record table includes: preferably, all the fail flags are processed for the row or column having the most common X-phase or Y-phase.
Preferably, the memory is a ferroelectric memory.
The invention also discloses a memory repair test system, which comprises a record table generating module, an analyzing module, a recording module and a processing module;
the record table generating module is used for generating an information statistic record table, and the data structure in the information statistic record table corresponds to the address information and the data information of the storage unit in the memory;
the analysis module is used for carrying out data analysis and address analysis on the memory to be tested through the test vector so as to obtain address information and data information of the failed storage unit in the memory;
the recording module is used for recording the address information of the failed storage unit and the corresponding data information into the information statistical recording table;
and the processing module is used for repairing the failed storage unit in the memory according to the information recorded in the information statistical record table after all the test vectors are executed.
Preferably, the data structure of the information statistics recording table includes X bits, Y bits, and Z bits, where the X bits and the Y bits respectively include a plurality of information bits corresponding to address information of storage units in a memory, and the Z bits include a plurality of information bits corresponding to data information in the storage units of the memory; and the recording module finds information bits corresponding to the X-bit and the Y-bit in the information statistical recording table according to the address information of the failed storage unit, makes a failure mark, and records the data information of the failed storage unit in the information bits in the Z-bit corresponding to the failure mark.
Preferably, the processing unit preferentially processes a row or a column with the most X-phase or Y-phase common to all the fail flags.
Preferably, the memory is a ferroelectric memory.
The invention also discloses a memory repair test system, which comprises:
one or more processors;
a memory;
and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing the memory repair test method as described above.
The invention also discloses a computer readable storage medium comprising a computer program for testing, the computer program being executable by a processor to perform the memory repair test method as described above.
Compared with the prior art, the memory repair test method adopts the information statistical record table to perform statistical record on the address information and the data information of the failed memory unit in the memory, records the information of the failed memory unit in the information statistical record table when some test vectors are not run in the test process, and performs repair processing on the failed memory unit in the memory according to the information recorded in the information statistical record table after all preset test vectors are executed; therefore, by adopting the memory repair test method, in the process of testing the memory by adopting a plurality of sections of test vectors, the middle part does not need to pause, and after all the test vectors are executed, all the failed memory units are repaired in a unified and orderly manner.
Drawings
FIG. 1 is a flow chart of a memory repair tester according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a two-dimensional data structure of an information statistics record table according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a two-dimensional data structure of an information statistics record table according to another embodiment of the present invention.
FIG. 4 is a schematic diagram of a two-dimensional data structure of an information statistics record table according to another embodiment of the present invention.
FIG. 5 is a system diagram of a memory repair test system according to an embodiment of the present invention.
Detailed Description
In order to explain technical contents, structural features, and objects and effects of the present invention in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
The embodiment discloses a memory repair test method, as shown in fig. 1, which includes the following steps:
s1: generating an information statistic record table, wherein the data structure in the information statistic record table corresponds to the address information and the data information of the storage unit in the memory, namely the information statistic record table can carry out statistic record on the address information and the data information of the storage unit in the memory;
s2: performing data analysis and address analysis on a memory to be tested through a test vector to obtain address information and data information of a failed storage unit in the memory; in this embodiment, a T5375 tester manufactured by the advantest corporation is used to perform data analysis and address resolution on the memory to be tested;
s3: recording the address information and the corresponding data information of the failed storage unit into an information statistical record table;
s4: and repeating the steps S2 and S3 until all the preset test vectors are executed, and then, uniformly repairing the failed storage units in the memory according to the information recorded in the information statistical record table.
Specifically, the information statistics recording table has a three-dimensional data structure including X-bit bits, Y-bit bits, and Z-bit bits, where the X-bit bits and the Y-bit bits respectively include a plurality of information bits corresponding to address information of storage units in the memory, and the Z-bit bits include a plurality of information bits corresponding to data information in the storage units in the memory. Then, when the information of the failed storage unit is recorded into the information statistics recording table, the information bits corresponding to the X-bit and the Y-bit are found in the information statistics recording table according to the address information of the failed storage unit and a failure mark is made, and the data information of the failed storage unit is recorded in the information bits in the Z-bit corresponding to the failure mark.
Since the Z-bit data information recorded in the statistics record table is the data information of the failed storage unit, and is irrelevant to the location retrieval of the failed storage unit, only the two-dimensional data structure diagram in the statistics record table is shown in fig. 2 to 4. Referring to fig. 2, if the row column number sequence of the address coordinates of the memory cells in the memory is 2048 × 127, each X-bit includes 127 information bits and each Y-bit includes 2027 information bits in the statistics record table. After a certain test vector is operated, through data analysis and address analysis of the memory to be tested, if two storage units with row and column numbers of (15,511) and (31,1023) are found to have errors, in the information statistics record table, two corresponding information bits are found by taking (15,511) and (31,1023) as coordinates and failure marks are made, namely X10 and X11 respectively, and corresponding data information is recorded in Y bits corresponding to the information bits X10 and X11 respectively. After the current test vector is run, another test vector can be run, like 3, through the running of the current test vector, five storage units are found to have errors, the failure marks in the information statistic record table are not marked as X20, X21, X22, X23 and X24, like 4, after the third test vector is run, three storage units are found to have errors, and the failure marks in the information statistic record table are not marked as X30, X31 and X32. After all the test vectors are executed, the memory is repaired according to the row and column information to which the failure marks (such as X10, X11, X20, X21, X22, X23, X24, X30, X31 and X32) recorded in the information statistic record table belong.
When the redundant unit is used for carrying out the replacement type repair processing on the memory unit with errors in the memory, the address replacement of the whole row or the whole column is carried out according to the address information, so in order to effectively improve the repair efficiency, the row or the column with the most X phase or the most Y phase shared by all the failure marks is preferentially processed. As shown in fig. 4, for ten failure flags in the information statistics record table, if the replacement operation of the entire row is performed on X20, X21, X10, X22, X23, and X24 in order, six replacement operations are required, if the replacement operation of the entire column is performed on X30, X31, X22, X11, and X32 in order, five replacement operations are required, and if the operation is performed in a manner of preferentially processing the row or the column having the most X phase or the most Y phase common to all the failure flags in this embodiment, among the ten bit failure flags, since X is concentrated on the 1023 th row and Y bit is concentrated on the 15 th column, only two replacement operations, that is, the replacement operation of the entire column is performed on X20, X21, X10, X22, X23, and X24, and then the replacement operation of the entire row is performed on X30, X31, X11, and X32, thereby increasing the processing efficiency.
Preferably, the memory in the above embodiment is a ferroelectric memory.
In summary, the present invention discloses a memory repair test method, which records address information and data information of an erroneous memory cell found in a test process by generating an information statistic record table, and is particularly suitable for a test environment in which a memory is tested for stability through multiple segments of test vectors, wherein only the test vectors are needed each time, only the found erroneous memory cell information is needed to be recorded in the information statistic record table, and when all the test vectors are executed, all the test data are directly obtained from the information statistic record table to perform corresponding repair data processing work, thereby effectively improving the test and repair efficiency of the memory.
In another embodiment of the present invention, a memory repair test system is further disclosed, as shown in fig. 5, which includes a record table generating module 10, an analyzing module 11, a recording module 12 and a processing module 13;
the record table generating module 10 is configured to generate an information statistics record table, where a data structure in the information statistics record table corresponds to address information and data information of a storage unit in a memory;
the analysis module 11 is configured to perform data analysis and address resolution on a memory to be tested through a test vector to obtain address information and data information of a failed storage unit in the memory;
the recording module 12 is configured to record the address information of the failed storage unit and the corresponding data information into the information statistics recording table;
and the processing module 13 is configured to, after all the test vectors are executed, perform repair processing on the failed storage unit in the memory according to the information recorded in the information statistics record table.
Further, the data structure of the information statistics recording table comprises an X bit, a Y bit and a Z bit, wherein the X bit and the Y bit respectively comprise a plurality of information bits corresponding to address information of storage units in a memory, and the Z bit comprises a plurality of information bits corresponding to data information in the storage units of the memory; the recording module 12 finds information bits corresponding to the X-bit and the Y-bit in the information statistics recording table according to the address information of the failed storage unit and makes a failure flag, and records the data information of the failed storage unit in the information bits in the Z-bit corresponding to the failure flag.
Preferably, the processing unit preferentially processes a row or a column with the most X-phase or Y-phase common to all the fail flags.
The working principle and the working process of the memory repair test system in this embodiment are described in detail in the above memory repair test method, and are not described herein again.
In another embodiment of the present invention, a memory repair test system is also disclosed, comprising one or more processors, memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing the memory repair test method as described above.
In another embodiment of the present invention, a computer readable storage medium is also disclosed, which includes a computer program for testing, the computer program being executable by a processor to perform the memory repair test method as described above.
The above disclosure is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the scope of the present invention, therefore, the present invention is not limited by the appended claims.
Claims (10)
1. A memory repair test method is characterized by comprising the following steps:
generating an information statistic record table, wherein the data structure in the information statistic record table corresponds to the address information and the data information of the storage unit in the memory;
performing data analysis and address analysis on a memory to be tested through the test vector to obtain address information and data information of a failed storage unit in the memory;
recording the address information and the corresponding data information of the failed storage unit into the information statistical record table;
and after all the test vectors are executed, repairing the failed storage unit in the memory according to the information recorded in the information statistical record table.
2. The memory repair test method of claim 1, wherein the data structure of the information statistics record table includes X bits, Y bits, and Z bits, the X bits and the Y bits respectively including a number of information bits corresponding to address information of the memory cells in the memory, respectively, the Z bits including a number of information bits corresponding to data information in the memory cells of the memory; when the information of the failure storage unit is recorded into the information statistics recording table, the information bits corresponding to the X-bit and the Y-bit are found in the information statistics recording table according to the address information of the failure storage unit, a failure mark is made, and the data information of the failure storage unit is recorded into the information bits in the Z-bit corresponding to the failure mark.
3. The memory repair test method according to claim 2, wherein the method for repairing the failed memory cell in the memory according to the information recorded in the information statistic record table includes: preferably, all the fail flags are processed for the row or column having the most common X-phase or Y-phase.
4. The memory repair test method of claim 1, wherein the memory is a ferroelectric memory.
5. A memory repair test system is characterized by comprising a record table generating module, an analyzing module, a recording module and a processing module;
the record table generating module is used for generating an information statistic record table, and the data structure in the information statistic record table corresponds to the address information and the data information of the storage unit in the memory;
the analysis module is used for carrying out data analysis and address analysis on the memory to be tested through the test vector so as to obtain address information and data information of the failed storage unit in the memory;
the recording module is used for recording the address information of the failed storage unit and the corresponding data information into the information statistical recording table;
and the processing module is used for repairing the failed storage unit in the memory according to the information recorded in the information statistical record table after all the test vectors are executed.
6. The memory repair test system of claim 5, wherein the data structure of the statistics record table comprises X bits, Y bits, and Z bits, the X bits and the Y bits respectively comprising a number of information bits corresponding to address information of the storage locations in the memory, the Z bits comprising a number of information bits corresponding to data information in the storage locations of the memory; and the recording module finds information bits corresponding to the X-bit and the Y-bit in the information statistical recording table according to the address information of the failed storage unit, makes a failure mark, and records the data information of the failed storage unit in the information bits in the Z-bit corresponding to the failure mark.
7. The memory repair test system of claim 6, wherein the processing unit preferentially processes a row or a column having a maximum X-phase or Y-phase common to all the fail flags.
8. The memory repair test system of claim 5, wherein the memory is a ferroelectric memory.
9. A memory repair test system, comprising:
one or more processors;
a memory;
and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing the memory repair test method of any of claims 1 to 4.
10. A computer-readable storage medium comprising a test computer program executable by a processor to perform the memory repair test method of any of claims 1 to 4.
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