CN113380314B - Memory repair test method and system - Google Patents
Memory repair test method and system Download PDFInfo
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- CN113380314B CN113380314B CN202110682992.0A CN202110682992A CN113380314B CN 113380314 B CN113380314 B CN 113380314B CN 202110682992 A CN202110682992 A CN 202110682992A CN 113380314 B CN113380314 B CN 113380314B
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- 230000015654 memory Effects 0.000 title claims abstract description 114
- 238000010998 test method Methods 0.000 title claims abstract description 23
- 238000012360 testing method Methods 0.000 claims abstract description 61
- 239000013598 vector Substances 0.000 claims abstract description 32
- 238000004458 analytical method Methods 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000007405 data analysis Methods 0.000 claims abstract description 9
- 238000004590 computer program Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000007547 defect Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000013112 stability test Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
The invention discloses a memory repair test method and a system, wherein the method comprises the following steps: generating an information statistics record table; performing data analysis and address analysis on the memory to be tested through the test vector to obtain address information and data information of a failure storage unit in the memory; recording address information of the failure storage unit and corresponding data information into an information statistics record table; after all the test vectors are executed, repairing the invalid storage unit in the memory according to the information recorded in the information statistics record table; by adopting the memory repair test method, in the process of testing the memory by adopting the multi-section test vectors, the middle part is not required to be stopped, and after all the test vectors are executed, all the failure memory units are uniformly and orderly repaired, so that the memory repair test method has the advantages of high test and repair efficiency and effectively saves test time.
Description
Technical Field
The invention relates to the technical field of memory repair detection, in particular to a high-efficiency memory repair test method and system.
Background
In the production test of the mainstream memory, some memories cannot realize normal memory functions because of the defect problem of the internal unit of the memories. In order to reduce the cost of the chip and improve the yield of the chip, a part of redundant memory units are reserved for replacing the faulty memory units when the chip is designed, so that the failure recovery is realized. In the process of testing, in order to ensure the storage performance of the memory to be stable, the tester often runs a plurality of test vectors, if the information of the FAIL exists in one test vector, the test vector is run once according to the traditional method, the information of the FAIL in the memory is stopped to be processed once, and if the number of the test vectors is too large, the required test time cost is high, so that the test efficiency is low.
Disclosure of Invention
The invention aims to provide a memory repair test method and a system capable of effectively improving the test efficiency of a memory chip in order to solve the defects of the technical problems.
In order to achieve the above purpose, the invention discloses a memory repair test method, comprising the following steps:
generating an information statistics record table, wherein a data structure in the information statistics record table corresponds to address information and data information of a storage unit in a memory;
Performing data analysis and address analysis on a memory to be tested through a test vector to obtain address information and data information of a failure storage unit in the memory;
The address information of the invalid storage unit and the corresponding data information are recorded into the information statistics record table;
and after all the test vectors are executed, repairing the invalid storage unit in the memory according to the information recorded in the information statistics record table.
Preferably, the data structure of the information statistics record table includes an X-bit, a Y-bit and a Z-bit, wherein the X-bit and the Y-bit respectively include a plurality of information bits respectively corresponding to address information of a storage unit in a memory, and the Z-bit includes a plurality of information bits corresponding to data information in the storage unit of the memory; when information of a failure storage unit is recorded into the information statistics recording table, information bits corresponding to an X bit and a Y bit are found in the information statistics recording table according to address information of the failure storage unit, failure marks are made, and data information of the failure storage unit is recorded in the information bits in a Z bit corresponding to the failure marks.
Preferably, the repairing method for the invalid storage unit in the memory according to the information recorded in the information statistics recording table includes: the most X-phase or Y-phase row or column common to all of the failure flags is preferentially processed.
Preferably, the memory is a ferroelectric memory.
The invention also discloses a memory repair test system, which comprises a record table generation module, an analysis module, a record module and a processing module;
The record table generation module is used for generating an information statistics record table, and the data structure in the information statistics record table corresponds to the address information and the data information of the storage unit in the memory;
The analysis module is used for carrying out data analysis and address analysis on the memory to be tested through the test vector so as to obtain the address information and the data information of the failure storage unit in the memory;
the recording module is used for recording the address information of the failure storage unit and the corresponding data information into the information statistics recording table;
And the processing module is used for repairing the invalid storage unit in the memory according to the information recorded in the information statistics record table after all the test vectors are executed.
Preferably, the data structure of the information statistics record table includes an X-bit, a Y-bit and a Z-bit, wherein the X-bit and the Y-bit respectively include a plurality of information bits respectively corresponding to address information of a storage unit in a memory, and the Z-bit includes a plurality of information bits corresponding to data information in the storage unit of the memory; and the recording module finds out information bits corresponding to the X bit and the Y bit in the information statistics recording table according to the address information of the failure storage unit, makes a failure mark, and records the data information of the failure storage unit in the information bits in the Z bit corresponding to the failure mark.
Preferably, the processing unit preferentially processes one row or one column with the most X-phase or Y-phase common to all the failure flags.
Preferably, the memory is a ferroelectric memory.
The invention also discloses a memory repair test system, which comprises:
one or more processors;
A memory;
And one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the memory repair test method as described above.
The invention also discloses a computer readable storage medium comprising a computer program for testing, the computer program being executable by a processor to perform a memory repair test method as described above.
Compared with the prior art, the memory repair test method adopts the information statistics record table to carry out statistics record on address information and data information of the invalid storage unit in the memory, and in the test process, some test vectors are not run, the information of the invalid storage unit is recorded in the information statistics record table, and after all preset test vectors are executed, repair processing is carried out on the invalid storage unit in the memory according to the information recorded in the information statistics record table; therefore, by adopting the memory repair test method, in the process of testing the memory by adopting the multi-section test vectors, the middle part is not required to be stopped, and after all the test vectors are executed, all the failure memory units are uniformly and orderly repaired, so that the memory repair test method has the advantages of high test and repair efficiency and effectively saves test time.
Drawings
FIG. 1 is a flow chart of a memory repair test method according to an embodiment of the invention.
FIG. 2 is a schematic diagram of a two-dimensional data structure of an information statistics table according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a two-dimensional data structure of an information statistics table according to another embodiment of the present invention.
FIG. 4 is a schematic diagram of a two-dimensional data structure of an information statistics table according to another embodiment of the present invention.
FIG. 5 is a system architecture diagram of a memory repair test system in accordance with an embodiment of the present invention.
Detailed Description
In order to describe the technical content, the constructional features, the achieved objects and effects of the present invention in detail, the following description is made in connection with the embodiments and the accompanying drawings.
The embodiment discloses a memory repair test method, as shown in fig. 1, comprising the following steps:
S1: generating an information statistics record table, wherein the data structure in the information statistics record table corresponds to the address information and the data information of the storage unit in the memory, namely the information statistics record table can carry out statistics record on the address information and the data information of the storage unit in the memory;
S2: carrying out data analysis and address analysis on the memory to be tested through a test vector to obtain address information and data information of a failure storage unit in the memory; in this embodiment, the data analysis and address resolution are performed on the memory to be tested by using a T5375 test machine manufactured by advantest company;
s3: recording address information of the failure storage unit and corresponding data information into an information statistics record table;
s4: and repeating the steps S2 and S3 until all the preset test vectors are executed, and then uniformly repairing the invalid storage units in the memory according to the information recorded in the information statistics record table.
Specifically, the information statistics record table has a three-dimensional data structure, including an X-bit, a Y-bit, and a Z-bit, where the X-bit and the Y-bit respectively include a plurality of information bits respectively corresponding to address information of a storage unit in the memory, and the Z-bit includes a plurality of information bits corresponding to data information in the storage unit in the memory. When the information of the invalid storage unit is recorded into the information statistics record table, information bits corresponding to the X bit and the Y bit are found in the information statistics record table according to the address information of the invalid storage unit, an invalid mark is made, and the data information of the invalid storage unit is recorded in the information bit in the Z bit corresponding to the invalid mark.
Since the Z-bit record of the information statistics table is the data information of the failed storage unit, the position search of the failed storage unit is irrelevant, and thus only the two-dimensional data structure diagrams in the information statistics table are shown in fig. 2 to 4. As shown in fig. 2, if the row and column number sequence of the address coordinates of the memory cells in the memory is 2048×127, each X-bit includes 127 information bits and each Y-bit includes 2027 information bits in the information statistics table. After running a certain test vector, through data analysis and address analysis of the memory to be tested, if two storage units with rank numbers (15,511) and (31,1023) are found to be wrong, two corresponding information bits are found in the information statistics record table by taking (15,511) and (31,1023) as coordinates, failure marks are made, namely X10 and X11 are respectively made, and data information corresponding to the information bits is recorded in Y bits corresponding to the information bits X10 and X11. After the current test vector is run, another test vector can be run next, as in 3, by running the current test vector, five storage units are found to have errors, failure marks in the information statistics record table are not marked as X20, X21, X22, X23 and X24, as in 4, when a third test vector is run, three storage units are found to have errors, and the failure marks in the information statistics record table are not marked as X30, X31 and X32. After all the test vectors are executed, the memory is uniformly repaired according to the row and column information of failure marks (such as X10, X11, X20, X21, X22, X23, X24, X30, X31 and X32) recorded in the information statistics record table.
When the redundant units are adopted to carry out replacement type repair processing on the memory units with errors in the memory, the whole row or the whole column of addresses are replaced according to the address information, so that the row or the column with the most X phase or Y phase shared by all failure marks is preferentially processed in order to effectively improve the repair efficiency. As shown in fig. 4, for ten failure flags in the information statistics recording table, if the entire row replacement operation is performed in order on X20, X21, X10, X22, X23, X24, six replacement operations are required, if the entire row replacement operation is performed in order on X30, X31, X22, X11, X32, five replacement operations are required, and if the operation is performed in such a manner that the one row or the one row having the most X phase or Y phase common to all the failure flags is processed according to the priority in the present embodiment, among the ten failure flags, since the X-bit is concentrated on 1023 th row and the Y-bit is concentrated on 15 th column, only the entire row replacement operation is performed, that is, the entire row replacement operation is performed on X20, X21, X10, X22, X23, X24, and then the entire row replacement operation is performed on X30, X31, X11, X32, thereby improving the processing efficiency.
Preferably, the memory in the above embodiment is preferably a ferroelectric memory.
In summary, the invention discloses a memory repair test method, which records address information and data information of a wrong memory unit found in a test process by generating an information statistics record table, is particularly suitable for a test environment for performing stability test on a memory by using a plurality of segments of test vectors, only needs to record the found wrong memory unit information in the information statistics record table each time, and directly acquires all test data from the information statistics record table when all the test vectors are executed, and performs corresponding repair data processing work, thereby effectively improving the test and repair efficiency of the memory.
In another embodiment of the present invention, as shown in fig. 5, a memory repair test system is disclosed, which includes a record table generating module 10, an analyzing module 11, a recording module 12 and a processing module 13;
the record table generating module 10 is configured to generate an information statistics record table, where a data structure in the information statistics record table corresponds to address information and data information of a storage unit in the memory;
The analysis module 11 is configured to perform data analysis and address analysis on a memory to be tested through a test vector, so as to obtain address information and data information of a failure storage unit in the memory;
the recording module 12 is configured to record address information of a failure storage unit and corresponding data information into the information statistics recording table;
and the processing module 13 is configured to repair the failed storage unit in the memory according to the information recorded in the information statistics record table after all the test vectors are executed.
Further, the data structure of the information statistics record table comprises an X-bit, a Y-bit and a Z-bit, wherein the X-bit and the Y-bit respectively comprise a plurality of information bits respectively corresponding to address information of a storage unit in a memory, and the Z-bit comprises a plurality of information bits corresponding to data information in the storage unit of the memory; the recording module 12 finds the information bit corresponding to the X bit and the Y bit in the information statistics recording table according to the address information of the invalid storage unit, makes an invalid mark, and records the data information of the invalid storage unit in the information bit in the Z bit corresponding to the invalid mark.
Preferably, the processing unit preferentially processes one row or one column with the most X-phase or Y-phase common to all the failure flags.
The working principle and working process of the memory repair test system in this embodiment are detailed in the above memory repair test method, and are not described herein.
In another embodiment of the invention, a memory repair test system is also disclosed that includes one or more processors, a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs including instructions for performing the memory repair test method as described above.
In another embodiment of the present invention, a computer readable storage medium is also disclosed, comprising a computer program for testing, the computer program being executable by a processor to perform a memory repair test method as described above.
The foregoing description of the preferred embodiments of the present invention is not intended to limit the scope of the claims, which follow, as defined in the claims.
Claims (6)
1. A memory repair test method, comprising the steps of:
generating an information statistics record table, wherein a data structure in the information statistics record table corresponds to address information and data information of a storage unit in a memory, the data structure of the information statistics record table comprises an X bit, a Y bit and a Z bit, the X bit and the Y bit respectively comprise a plurality of information bits respectively corresponding to the address information of the storage unit in the memory, and the Z bit comprises a plurality of information bits corresponding to the data information in the storage unit of the memory;
Performing data analysis and address analysis on a memory to be tested through a test vector to obtain address information and data information of a failure storage unit in the memory;
Recording address information and corresponding data information of a failure storage unit into the information statistics recording table, finding information bits corresponding to an X bit and a Y bit in the information statistics recording table according to the address information of the failure storage unit, making a failure mark, and recording the data information of the failure storage unit into the information bits in a Z bit corresponding to the failure mark;
And after all the test vectors are executed, repairing the invalid storage units in the memory according to the information recorded in the information statistics record table, and preferentially processing one row or one column with the most X phase or Y phase shared by all the invalid marks.
2. The memory repair test method according to claim 1, wherein the memory is a ferroelectric memory.
3. The memory repair test system is characterized by comprising a record table generation module, an analysis module, a record module and a processing module;
the record table generation module is used for generating an information statistics record table, the data structure in the information statistics record table corresponds to the address information and the data information of the storage unit in the memory, the data structure of the information statistics record table comprises an X bit, a Y bit and a Z bit, the X bit and the Y bit respectively comprise a plurality of information bits respectively corresponding to the address information of the storage unit in the memory, and the Z bit comprises a plurality of information bits respectively corresponding to the data information in the storage unit of the memory;
The analysis module is used for carrying out data analysis and address analysis on the memory to be tested through the test vector so as to obtain the address information and the data information of the failure storage unit in the memory;
The recording module is used for recording the address information of the failure storage unit and the corresponding data information into the information statistics recording table, finding out information bits corresponding to the X bit and the Y bit in the information statistics recording table according to the address information of the failure storage unit, making a failure mark, and recording the data information of the failure storage unit in the information bits in the Z bit corresponding to the failure mark;
And the processing module is used for repairing the invalid storage unit in the memory according to the information recorded in the information statistics record table after all the test vectors are executed, and the processing module preferentially processes one row or one column with the most X phase or Y phase shared by all the invalid marks.
4. The memory repair test system according to claim 3, wherein the memory is a ferroelectric memory.
5. A memory repair test system, comprising:
one or more processors;
A memory;
And one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the one or more processors, the programs comprising instructions for performing the memory repair test method of any of claims 1-2.
6. A computer readable storage medium comprising a computer program for testing, the computer program being executable by a processor to perform the memory repair test method of any one of claims 1 to 2.
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