CN107039084A - The crystal round test approach of memory chip with redundancy unit - Google Patents
The crystal round test approach of memory chip with redundancy unit Download PDFInfo
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- CN107039084A CN107039084A CN201710116685.XA CN201710116685A CN107039084A CN 107039084 A CN107039084 A CN 107039084A CN 201710116685 A CN201710116685 A CN 201710116685A CN 107039084 A CN107039084 A CN 107039084A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/006—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation at wafer scale level, i.e. wafer scale integration [WSI]
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/702—Masking faults in memories by using spares or by reconfiguring by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention discloses a kind of crystal round test approach of the memory chip with redundancy unit, including step：Step 1: in the structure setting memory test machine of the array structure of the main region of memory chip on wafer and redundancy unit storage fail address memory row address and the length of column address；Step 2: chip unit is tested, and by the memory that row address identical storage fail address is stored after the test result progress or computing of every a line；Step 3: the content for reading each row in the memory of storage fail address draws the line number and row address of failure；Step 4: can judge the row of each failure of the main region of memory chip repair, if then distribution redundancy unit replaces the failure row of the main region of memory chip.The present invention can effectively reduce the testing time, reduce testing cost.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, more particularly to a kind of depositing with redundancy unit
The crystal round test approach of memory chip.
Background technology
Wafer sort (Circuit Probing, CP) is also referred to as the survey of circuit pin, is before packaging directly at wafer (wafer)
On chip die (die) is tested, for verifying whether each chip meets product specification.
In order to improve when at present when testing memory chip (Memory IC) to memory chip progress wafer sort
Yields is tested, redundancy unit (Redundancy Sector) can be increased, effect is to work as to detect chip main region (main
When array) having disabling unit (fail bit cell), the disabling unit of main region, replacement side can be replaced with redundancy unit
Formula typically has hardware replacement and software to replace two kinds, and present more common method is that software is replaced.
This kind of chip is tested to generally require with special memory test machine (Memory Tester), because memory
Test machine can carry a kind of special random access memory (RAM), for storing the address of chip under test (DUT) disabling unit, one
As abbreviation ECR or AFM.This block RAM can record the disabling unit address of the accumulative test of the test item of each in testing process, generally
The BIT addresses of ECR or AFM position (BIT) address correspondence chip under test are one-to-one in use, so by defining ECR
Or AFM X or Y address length, it can test and draw every chip status figure (BITMAP), then read each ECR's or AFM
BIT MAP address dates, calculate disabling unit address with algorithm, and flow finally count the summation of disabling unit number with
And fail address, replace disabling unit with redundancy unit.But this method needs to read BIT MAP repeatedly, then does algorithm fortune
Calculate, it is inefficient with surveying because reading and algorithm operating belong to serial operation in bus, if test is high with survey number,
Testing time can be very long, causes testing cost too high, so how to reduce the testing time with redundancy unit chip becomes
The huge challenge of Test Engineer.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of wafer sort side of the memory chip with redundancy unit
Method, can effectively reduce the testing time, reduce testing cost.
In order to solve the above technical problems, the crystal round test approach bag for the memory chip with redundancy unit that the present invention is provided
Include following steps：
Step 1: being stored according to the structure setting of the array structure of the main region of memory chip and redundancy unit on wafer
The row address and the length of column address of the memory of storage fail address in device test machine, the main region of the memory chip
Array structure be structure that M rows N is arranged, M and N are integer；The redundancy unit is the structure that 1 row N is arranged, the storage failure
The length of the row address of the memory of address is M, and the length of column address is 1.
Step 2: being surveyed using the memory test machine to each chip unit of the main region of the memory chip
Examination, and storage after the test result progress or computing of every a line is arrived to the memory that fail address is stored described in row address identical
In.
Step 3: the content for reading each row in the memory of the storage fail address draws the line number and row of failure
Address.
Step 4: can judge the row of each failure of the main region of the memory chip repair, if then distributing described
Redundancy unit replaces the failure row of the main region of the memory chip.
Further improve is that the memory of the storage fail address in the memory test machine is ECR or AFM.
Further improve be, to the item of the test of each chip unit of the main region of the memory chip in step 2
Mesh is included more than once.
Further improve be, each chip unit of the main region to the memory chip of step 2 carry out each
Need to be configured test vector in test so that often read a line chip unit of the main region of the memory chip
Row address carry is just done afterwards.
Further improve is to carry out the test result of every a line in step 2 or computing includes：
By the test result of each mutually every chip unit of colleague of each test carry out or computing obtain one it is corresponding
Or operation result.
By the item mutually gone together of different test events is corresponding or operation result is carried out or computing obtains overall or computing
As a result.
Further improve be, loses overall or operation result storage to being stored described in row address identical in step 2
In the memory for imitating address.
Further improve is that each chip unit of the main region of the memory chip is tested in step 2,
The test result of normal chip unit is " 0 ", and the test result of the chip unit of failure is " 1 ", the storage fail address
Memory in the value of corresponding row storage represent when being " 1 " the corresponding memory chip of row address main region row
Represent capable when the value of corresponding row storage is " 0 " in the middle chip unit that there is failure, the memory of the storage fail address
Chip unit in the row of the main region of the corresponding memory chip in address is all normal.
Further improve is will to be deposited in step 4 using hardware or software substitute mode described in redundancy unit replacement
The failure row of the main region of memory chip.
The present invention passes through the structure setting according to the array structure of the main region of memory chip and redundancy unit on wafer
The row address and the length of column address of the memory of storage fail address in memory test machine, have used redundancy unit
Structure is identical with the structure of a line of the array structure of the main region of memory chip, and it is to use redundancy list to carry out when failure is replaced
The characteristics of member replaces a line with the array structure of the main region of memory chip so that the storage in memory test machine is lost
The memory of address is imitated no longer using the one-to-one structure of each bit address with the array structure of the main region of memory chip,
But the main region of the row address and memory chip only with the memory of the storage fail address in memory test machine
The length of the column address of the memory of storage fail address in the corresponding structure of row address of array structure, memory test machine
It is set to 1.
And in On-Wafer Measurement, test progress or computing in same a line that each test is obtained are then stored in storage
In a line of the memory of fail address, or the result of computing only has one, therefore row length is the storage of 1 storage fail address
Device can store last test result.
From the test result in the memory for being stored in storage fail address as can be seen that the inventive method is greatly reduced
Amount of storage, so that the memory for adding storage fail address is usually the service efficiency of ECR or AFM module.
And store the reduction of the quantity of result so that the memory for storing fail address is read during follow-up progress redundancy replacement
The time taken greatly reduces, i.e., only need to read one per a line, so the testing time can be caused to greatly reduce, and test effect
Rate is then greatly improved, in semiconductor integrated circuit manufacture, Time is money, so the present invention can finally substantially reduce test
Cost.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the array junctions composition of the main region of memory chip on wafer；
Fig. 2 is the structure chart of redundancy unit；
Fig. 3 is flow of the crystal round test approach to ECR or AFM reading of the existing memory chip with redundancy unit
Figure；
Fig. 4 is the flow chart of the crystal round test approach of memory chip of the embodiment of the present invention with redundancy unit；
Fig. 5 is the crystal round test approach corresponding ECR or AFM of memory chip of the embodiment of the present invention with redundancy unit
Storage figure；
Fig. 6 be memory chip of the embodiment of the present invention with redundancy unit crystal round test approach in reading to ECR or AFM
The flow chart taken.
Embodiment
A little description below first are done to the measuring mechanism of existing memory test machine calibration tape redundancy feature chip：
This kind of chip is tested to generally require with special memory test machine, because memory test chance is with one kind
Special RAM, for storing the address of chip under test (DUT) disabling unit, general abbreviation ECR or AFM.A simple case is lifted,
As shown in figure 1, be the array junctions composition of the main region of memory chip on wafer, certain memory chip by the unit of X addresses 10,
8 unit compositions of Y address, X addresses are defined as column address, and Y is defined as row address；And redundancy unit unit is a line, i.e. X-direction
10 units, 1 unit of Y-direction, the structure chart of redundancy unit refer to shown in Fig. 2.Because redundancy unit least unit is capable,
As long as so there is element failure in a row, this row is just judged as failure, is repaired with redundancy unit.In actual test mistake
Cheng Zhong, ECR can record the disabling unit address of the accumulative test of the test item of each in testing process, and existing method is remembered in ECR
The graphic structure of the test result of record and the array junctions composition of the main region of memory chip are one-to-one, i.e., one tests
As a result the test result of the record recorded in a chip unit of the main region of memory chip, this existing ECR is corresponded to
Graphic structure be BITMAP, so the BITMAP figure and Fig. 1 be identical.
Carrying out redundancy replacement needs to be read out ECR, first finds quantity and the address of corresponding disabling unit, then
Redundancy replacement is carried out again, as shown in figure 3, being the crystal round test approach of the existing memory chip with redundancy unit to ECR or AFM
Reading flow chart；As can be seen that when reading figure, it is first reading Y address i.e. row address, then to the X in same a line
Location is that column address is changed, and reads the data of each, and every data of same a line are carried out or computing, is read with a line
Increase the reading that Y address realizes subsequent cycle after finishing, until circulation terminates, read namely finish.As can be seen that described in Fig. 3
Test program can be read by Y address each X address ECR storage content, by taking 8 × 10 shown in Fig. 1 array as an example, chip
Read 8X10=80 unit；, it is necessary to serially read the ECR contents of each chip when running into survey." 0 " represents and not had in ECR
There is failure, " 1 " represents failure, also need to do each row of data or computing after reading every data, draw the line number and row of failure
Address, judges whether to repair, if then distribution redundancy unit replaces failure row unit, to ensure that test is used after passing through to rear end
Chip at family is non-defective unit.
Above is memory test machine with ECR come the measuring mechanism of calibration tape redundancy feature chip, but when chip under test hold
When amount is very big, the content of ECR storages will become very big, it is meant that reading the time of ECR contents every time will lengthen.
As shown in figure 4, be the flow chart of the crystal round test approach of memory chip of the embodiment of the present invention with redundancy unit,
The crystal round test approach of memory chip of the embodiment of the present invention with redundancy unit comprises the following steps：
Step 1: being stored according to the structure setting of the array structure of the main region of memory chip and redundancy unit on wafer
The row address and the length of column address of the memory of storage fail address in device test machine, the main region of the memory chip
Array structure be structure that M rows N is arranged, M and N are integer, and M here is the array structure of the main region of memory chip
Actual line number, N is actual columns；The schematic diagram of the array structure of the main region of the memory chip refer to Fig. 1 institutes
Show, in Fig. 1 by 8, N of M be 9 exemplified by illustrate, row address is represented with 0 to 7 respectively, and column address is represented with 0 to 9 respectively.
The redundancy unit is the structure that 1 row N is arranged, and be refer to shown in Fig. 2.
The length of the row address of the memory of the storage fail address is M, and the length of column address is 1, refer to Fig. 5 institutes
Show.
The memory of storage fail address in the memory test machine is ECR or AFM, namely uses the memory
The ECR or AFM that test machine has in itself are used as the memory for storing fail address.
Step 2: being surveyed using the memory test machine to each chip unit of the main region of the memory chip
Examination, and storage after the test result progress or computing of every a line is arrived to the memory that fail address is stored described in row address identical
In.
Project to the test of each chip unit of the main region of the memory chip is included more than once.Deposited to described
Need to be configured test vector in each test that each chip unit of the main region of memory chip is carried out so that often read
Row address carry is just done after a line chip unit of the main region of the complete memory chip.
The test result of every a line is carried out or computing includes：
By the test result of each mutually every chip unit of colleague of each test carry out or computing obtain one it is corresponding
Or operation result.Lost as shown in figure 1, all being crossed at the position of the 3rd, 4,6 row of wherein the 2nd row and representing corresponding chip unit
Effect, can successively be tested the every of same a line, normal chip unit when being tested using the memory test machine
Test result be " 0 ", the test result of the chip unit of failure is " 1 ", and test result is carried out or computing afterwards, can be seen
Go out, chip unit of second row due to occurring in that 3 failures, if this test result can be by the chip list of this 3 failures
Member is all detected, obtained structure will respectively 1, therefore every test result of the 2nd row carry out or computing after obtained test
The corresponding or operation result of item is 1.
Generally, the project to the test of each chip unit of the main region of the memory chip is included more than once, has
A little disabling units into some test events possibly through, therefore finally need the item mutually gone together of different test events is right
Answer or operation result is carried out or computing obtains overall or operation result.Finally, the overall or operation result obtained is：The
The value of 2 rows and the 5th row is 1, and other rows are corresponding to be worth all for 0.Afterwards, it is overall or operation result storage is identical to row address
The storage fail address memory in and obtain only needing the storage battle array that is arranged using 8 rows 1 in the storage figure shown in Fig. 5, Fig. 5
Row can just meet the storage of test result, no longer be the one of the array structure of shown in Fig. 1 and memory chip main region
One corresponding relation.And it is only the corresponding relation of row, and in Fig. 5, corresponding row storage in the memory of the storage fail address
It is worth the chip unit that there is failure in the row for the main region that the row address corresponding memory chip is represented during for " 1 ", institute
The value for stating corresponding row storage in the memory of storage fail address represents the corresponding storage core of row address when being " 0 "
Chip unit in the row of the main region of piece is all normal.
Compare and understood shown in Fig. 5 and Fig. 1, present invention method greatly reduces amount of storage, so as to add storage
The memory of fail address is usually the service efficiency of ECR or AFM module.
Step 3: the content for reading each row in the memory of the storage fail address draws the line number and row of failure
Address.As shown in fig. 6, be memory chip of the embodiment of the present invention with redundancy unit crystal round test approach in ECR or AFM
Reading flow chart, it can be seen that have 1 because X addresses only have, thus only need carry out Y address circulation, moreover, this
In inventive embodiments method, the corresponding storage value of each row is that same a line or computing result has been carried out, therefore in the present invention
Test result that need not be again to same a line in the reading flow of embodiment method is carried out or computing.
By taking the array architecture shown in Fig. 1 as an example, present invention method only needs 8 readings of progress to can be achieved, relatively
72 readings are reduced in existing method；In addition, present invention method also saves substantial amounts of or computing time；So
Present invention method can cause the testing time to greatly reduce, and testing efficiency is then greatly improved, in semiconductor integrated circuit
In manufacture, Time is money, so can finally substantially reduce testing cost.Particularly when synchronous detecting number increase, the present invention
Embodiment method is more obvious to the effect of the reduction of testing time.
Step 4: can judge the row of each failure of the main region of the memory chip repair, if then distributing described
Redundancy unit replaces the failure row of the main region of the memory chip.In present invention method, using software replacement side
Formula replaces the redundancy unit failure row of the main region of the memory chip.In other embodiments method, it can also adopt
The redundancy unit is replaced to the failure row of the main region of the memory chip with hardware replacement mode.
The present invention is described in detail above by specific embodiment, but these not constitute the limit to the present invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (8)
1. a kind of crystal round test approach of the memory chip with redundancy unit, it is characterised in that comprise the following steps：
Step 1: being surveyed according to the structure setting memory of the array structure of the main region of memory chip on wafer and redundancy unit
The row address and the length of column address of the memory of storage fail address in test-run a machine, the battle array of the main region of the memory chip
Array structure is the structure that M rows N is arranged, and M and N are integer；The redundancy unit is the structure that 1 row N is arranged, the storage fail address
The length of row address of memory be M, the length of column address is 1；
Step 2: each chip unit of the main region of the memory chip is tested using the memory test machine,
And will be stored after the test result progress or computing of every a line in the memory that fail address is stored described in row address identical；
Step 3: the content for reading each row in the memory of the storage fail address draws the line number and row ground of failure
Location；
Step 4: can judge the row of each failure of the main region of the memory chip repair, if then distributing the redundancy
Unit replaces the failure row of the main region of the memory chip.
2. the crystal round test approach of the memory chip as claimed in claim 1 with redundancy unit, it is characterised in that：It is described to deposit
The memory of storage fail address in reservoir test machine is ECR or AFM.
3. the crystal round test approach of the memory chip as claimed in claim 1 with redundancy unit, it is characterised in that：Step 2
In the project of the test of each chip unit of the main region of the memory chip is included more than once.
4. the crystal round test approach of the memory chip as claimed in claim 3 with redundancy unit, it is characterised in that：Step 2
The main region to the memory chip each chip unit carry out each test in need to be configured test vector,
So that just doing row address carry after often having read a line chip unit of the main region of the memory chip.
5. the crystal round test approach of the memory chip as claimed in claim 4 with redundancy unit, it is characterised in that：Step 2
The middle test result by every a line is carried out or computing includes：
The test result of each mutually every chip unit of colleague of each test is carried out or computing obtains a corresponding or fortune
Calculate result；
By the item mutually gone together of different test events is corresponding or operation result is carried out or computing obtains overall or operation result.
6. the crystal round test approach of the memory chip as claimed in claim 5 with redundancy unit, it is characterised in that：Step 2
It is middle by overall or operation result storage into the memory for storing fail address described in row address identical.
7. the crystal round test approach of the memory chip with redundancy unit as described in claim 1 or 5 or 6, it is characterised in that：
Each chip unit of the main region of the memory chip is tested in step 2, the test result of normal chip unit
For " 0 ", the test result of the chip unit of failure is corresponding row storage in " 1 ", the memory of the storage fail address
It is worth the chip unit that there is failure in the row for the main region that the row address corresponding memory chip is represented during for " 1 ", institute
The value for stating corresponding row storage in the memory of storage fail address represents the corresponding storage core of row address when being " 0 "
Chip unit in the row of the main region of piece is all normal.
8. the crystal round test approach of the memory chip as claimed in claim 1 with redundancy unit, it is characterised in that：Step 4
Middle use hardware or software substitute mode replace the redundancy unit failure row of the main region of the memory chip.
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| WO2021142816A1 (en) * | 2020-01-19 | 2021-07-22 | 华为技术有限公司 | Wafer to wafer structure and test method therefor, and high bandwidth memory and manufacturing method therefor |
| CN113380314A (en) * | 2021-06-18 | 2021-09-10 | 广东利扬芯片测试股份有限公司 | Memory repair test method and system |
| CN114171103A (en) * | 2020-09-11 | 2022-03-11 | 长鑫存储技术有限公司 | Method for determining repair scheme of failed bit |
| US11776654B2 (en) | 2020-09-11 | 2023-10-03 | Changxin Memory Technologies, Inc. | Fail bit repair solution determination method and device |
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| CN113380314B (en) * | 2021-06-18 | 2024-05-14 | 广东利扬芯片测试股份有限公司 | Memory repair test method and system |
| US11978504B2 (en) | 2022-03-23 | 2024-05-07 | Changxin Memory Technologies, Inc. | Method and apparatus for determining sense boundary of sense amplifier, medium, and device |
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